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參數(shù)資料
| 型號(hào)： | DS3184 |
| 廠商： | Maxim Integrated Products |
| 文件頁(yè)數(shù)： | 47/400頁(yè) |
| 文件大?。?/td> | 0K |
| 描述： | IC QUAD ATM/PACKET PHY 400-PBGA |
| 產(chǎn)品培訓(xùn)模塊： | Lead (SnPb) Finish for COTS Obsolescence Mitigation Program |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 類型： | 調(diào)幀器 |
| 應(yīng)用： | 數(shù)據(jù)傳輸 |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 400-BBGA |
| 供應(yīng)商設(shè)備封裝： | 400-PBGA（27x27） |
| 包裝： | 管件 |
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DS3181/DS3182/DS3183/DS3184
140
10.7.2.2 ATM Cell Processor
Programmable HEC insertion and extraction – The transmit side can be programmed to accept cells from
the system interface that do or do not contain a HEC byte. If cells are transferred without a HEC byte, the HEC
byte will be computed and inserted. If cells are transferred with a HEC byte, then the transferred HEC byte can
be programmed to be passed through or overwritten with a newly calculated HEC. The receive side can be
programmed to send cells to the system interface that do or don't contain the HEC byte.
Programmable erred cell insertion – An HEC error mask can be programmed for insertion of single or
multiple errors individually or continuously at a programmable rate.
Programmable transmit cell synchronization – The transmit data line can be provisioned to be bit
synchronous or octet aligned.
PLCP or HEC based cell delineation – Cell delineation is determined from the PLCP frame during PLCP
framing modes, and from the HEC during all other ATM modes.
Programmable header cell pass-through – Receive cell filtering can pass-through only those cells that
matching a programmable header value.
Selectable idle/unassigned/invalid/programmable header cell padding and filtering – Transmit cell
padding can be programmed for idle cell or programmable header cell padding. The padded cell payload byte
contents are also programmable. Receive cell filtering can be programmed for any combination of idle cell,
unassigned cell, invalid cell, or programmable header cell filtering. Or, all cell filtering can be disabled.
Optional header error correction – Receive side single bit header error correction can enabled.
Separate corrected and uncorrected erred cell counts – Separate counts of erred cells containing a
corrected HEC error, and cells containing non-corrected HEC errors are kept.
Optional HEC uncorrected erred cell filtering – Uncorrected erred cell extraction can be disabled.
Selectable cell scrambling/descrambling – Cell scrambling and/or descrambling can be disabled. The
scrambling can be a self-synchronous scrambler (x
43 + 1) over the payload only, a self-synchronous scrambler
over the entire cell, or a Distributed Sample Scrambler (x
31 + x28 + 1).
Optional HEC calculation coset polynomial addition – The performance of coset polynomial addition during
HEC calculation can be disabled.
10.7.2.3 HDLC Packet Processor
Programmable FCS insertion and extraction – The transmit side can be programmed to accept packets
from the system interface that do or don't contain FCS bytes. If packets are transferred without FCS bytes, the
FCS will be computed and appended to the packet. If packets are transferred with FCS bytes, then the FCS
can be programmed to be passed through or overwritten with a newly calculated FCS. The receive side can be
programmed to send packets to the system interface that do or don't contain FCS bytes.
Programmable transmit packet synchronization – The transmit data line can be provisioned to be bit
synchronous or octet aligned.
Programmable FCS type – The FCS can be programmed to be a 16-bit FCS or a 32-bit FCS.
Supports FCS error insertion – FCS error insertion can be programmed for insertion of errors individually or
continuously at a programmable rate.
Supports bit or byte stuffing/destuffing – The bit or byte synchronous (octet aligned) mode determines the
bit or byte stuffing/destuffing.
Programmable packet size limits – The receive side can be programmed to abort packets over a
programmable maximum size or under a programmable minimum size. The maximum packet size allowed is
65,535 bytes.
Selectable packet scrambling/descrambling – Packet scrambling and/or descrambling can be disabled.
Separate FCS erred packet and aborted packet counts – Separate counts of aborted packets, size violation
packets, and FCS erred packets are kept.
Optional erred packet filtering – Erred packet extraction can be disabled
Programmable inter-frame fill – The transmit inter-frame fill value is programmable.
10.7.3 Transmit Cell/Packet Processor
The Transmit Cell Processor and Transmit Packet Processor both receive the 32-bit parallel data stream from the
Transmit FIFO, however, only one of the processors will be enabled. Which processor is enabled is determined by
the system interface mode. In UTOPIA mode, the Transmit Cell Processor is enabled. In POS-PHY mode, if the
PORT.CR2.PMCPE bit is low, the Transmit Packet Processor is enabled. If the PORT.CR2.PMCPE bit
(PORT.CR2) is high, the Transmit Cell Processor is enabled.
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
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| DS3184+ | 功能描述:網(wǎng)絡(luò)控制器與處理器 IC Quad ATM/Packet PHYs w/Built-In LIU RoHS:否 制造商:Micrel 產(chǎn)品:Controller Area Network (CAN) 收發(fā)器數(shù)量: 數(shù)據(jù)速率: 電源電流（最大值）:595 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:PBGA-400 封裝:Tray |
| DS3184DK | 功能描述:網(wǎng)絡(luò)開發(fā)工具 RoHS:否 制造商:Rabbit Semiconductor 產(chǎn)品:Development Kits 類型:Ethernet to Wi-Fi Bridges 工具用于評(píng)估:RCM6600W 數(shù)據(jù)速率:20 Mbps, 40 Mbps 接口類型:802.11 b/g, Ethernet 工作電源電壓:3.3 V |
| DS3184N | 功能描述:網(wǎng)絡(luò)控制器與處理器 IC Quad ATM/Packet PHYs w/Built-In LIU RoHS:否 制造商:Micrel 產(chǎn)品:Controller Area Network (CAN) 收發(fā)器數(shù)量: 數(shù)據(jù)速率: 電源電流（最大值）:595 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:PBGA-400 封裝:Tray |
| DS3184N+ | 功能描述:網(wǎng)絡(luò)控制器與處理器 IC Quad ATM/Packet PHYs w/Built-In LIU RoHS:否 制造商:Micrel 產(chǎn)品:Controller Area Network (CAN) 收發(fā)器數(shù)量: 數(shù)據(jù)速率: 電源電流（最大值）:595 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:PBGA-400 封裝:Tray |
| DS318PIN | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Industrial Control IC |
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