參數(shù)資料
型號: DS3154N+
廠商: Maxim Integrated Products
文件頁數(shù): 30/61頁
文件大?。?/td> 0K
描述: IC LIU DS3/E3/STS-1 QD 144CSBGA
產(chǎn)品培訓(xùn)模塊: Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
標(biāo)準(zhǔn)包裝: 160
類型: 線路接口裝置(LIU)
驅(qū)動器/接收器數(shù): 4/4
規(guī)程: IEEE 1149.1
電源電壓: 3.135 V ~ 3.465 V
安裝類型: 表面貼裝
封裝/外殼: 144-BGA,CSPBGA
供應(yīng)商設(shè)備封裝: 144-TECSBGA(13x13)
包裝: 管件
DS3151/DS3152/DS3153/DS3154 Single/Dual/Triple/Quad DS3/E3/STS-1 LIUs
36 of 61
12.4
JTAG Test Registers
IEEE 1149.1 requires a minimum of two test registers—the bypass register and the boundary scan register. An
optional test register, the identification register, has been included in the device design. It is used with the IDCODE
instruction and the Test-Logic-Reset state of the TAP controller.
Bypass Register. This single 1-bit shift register, used with the BYPASS, CLAMP, and HIGHZ instructions,
provides a short path between JTDI and JTDO.
Boundary Scan Register. This register contains a shift register path and a latched parallel output for control cells
and digital I/O cells. DS315x BSDL files are available at www.maxim-ic.com/TechSupport/telecom/bsdl.htm.
Identification Register. This register contains a 32-bit shift register and a 32-bit latched parallel output. It is
selected during the IDCODE instruction and when the TAP controller is in the Test-Logic-Reset state.
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