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參數(shù)資料
| 型號： | DS3150Q+T&R |
| 廠商： | Maxim Integrated Products |
| 文件頁數(shù)： | 8/28頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC LIU DS3/E3/STS-1 28-PLCC |
| 產(chǎn)品培訓(xùn)模塊： | Lead (SnPb) Finish for COTS Obsolescence Mitigation Program |
| 標(biāo)準(zhǔn)包裝： | 500 |
| 類型： | 線路接口裝置（LIU） |
| 驅(qū)動器/接收器數(shù)： | 1/1 |
| 規(guī)程： | DS3 |
| 電源電壓： | 3.135 V ~ 3.465 V |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 28-LCC（J 形引線） |
| 供應(yīng)商設(shè)備封裝： | 28-PLCC（11.51x11.51） |
| 包裝： | 帶卷 (TR) |
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DS3150
16 of 28
1.4 Jitter Attenuator
The DS3150 contains an on-board jitter attenuator (JA) that can be placed in the receive path or in the
transmit path or disabled. This selection is made using the RMON and
TTS input pins. See Table 2-C for
selection details. Figure 1-8 shows the minimum jitter attenuation for the device when the JA is enabled.
Figure 1-8 also shows the jitter transfer of the receiver when the JA is disabled.
The jitter attenuator consists of a narrowband PLL to retime the selected clock, a 16 x 2-bit FIFO to
buffer the associated data while the clock is being retimed, and logic to prevent over/underflow of the
FIFO in the presence of very large jitter amplitudes.
The jitter attenuator requires a transmission-quality master clock (i.e.,
±20ppm frequency accuracy and
low jitter). When enabled in the receive path, the JA can obtain its master clock from the MCLK pin or
the TCLK pin. If the signal on the MCLK pin is toggling, the JA uses the signal on MCLK as its master
clock. If MCLK is high or floating, the JA uses the signal on the TCLK pin as its master clock. When
enabled in the transmit path, the JA must take its master clock from the MCLK pin. The selected master
clock is also used by the clock and data recovery block.
The JA has a loop bandwidth of master_clock / 2058874 (see corner frequencies in Figure 1-8). The JA
attenuates jitter at frequencies higher than the loop bandwidth while allowing jitter (and wander) at lower
frequencies to pass through relatively unaffected.
Figure 1-8. Jitter Attenuation and Jitter Transfer
10
100
1k
10k
100k
1M
21.7Hz (DS3)
16.7Hz (E3)
25.2Hz (STS-1)
1k
-30
-20
-10
E3 [TBR24 (1997)]
Frequency (Hz)
Jitter
Attenuation
(dB)
0
DS3 [GR-499 (1995)]
Category I
DS3150
Typical
Receiver Jitter
Transfer with
Jitter Attenuator
Disabled
>150k
DS3150
DS3 / E3 / STS-1
Minimum Jitter
Attenuation with
Jitter Attenuator
Enabled
40Hz
DS3 [GR-253 (1999)]
Category I
27Hz
STS-1
[GR-253 (1999)]
Category II
40k 59.6k
DS3 [GR-499 (1999)]
Category II
NOTE: JITTER ATTENUATION AND JITTER TRANSFER ARE NOT TESTED DURING PRODUCTION TEST.
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| DS3150T | 功能描述:網(wǎng)絡(luò)控制器與處理器 IC 3.3V DS3/E3/STS-1 Line Interface Unit RoHS:否 制造商:Micrel 產(chǎn)品:Controller Area Network (CAN) 收發(fā)器數(shù)量: 數(shù)據(jù)速率: 電源電流（最大值）:595 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:PBGA-400 封裝:Tray |
| DS3150T+ | 功能描述:網(wǎng)絡(luò)控制器與處理器 IC 3.3V DS3/E3/STS-1 Line Interface Unit RoHS:否 制造商:Micrel 產(chǎn)品:Controller Area Network (CAN) 收發(fā)器數(shù)量: 數(shù)據(jù)速率: 電源電流（最大值）:595 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:PBGA-400 封裝:Tray |
| DS3150TC1 | 功能描述:網(wǎng)絡(luò)控制器與處理器 IC 3.3V DS3/E3/STS-1 Line Interface Unit RoHS:否 制造商:Micrel 產(chǎn)品:Controller Area Network (CAN) 收發(fā)器數(shù)量: 數(shù)據(jù)速率: 電源電流（最大值）:595 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:PBGA-400 封裝:Tray |
| DS3150TC1+ | 功能描述:網(wǎng)絡(luò)控制器與處理器 IC 3.3V DS3/E3/STS-1 Line Interface Unit RoHS:否 制造商:Micrel 產(chǎn)品:Controller Area Network (CAN) 收發(fā)器數(shù)量: 數(shù)據(jù)速率: 電源電流（最大值）:595 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:PBGA-400 封裝:Tray |
| DS3150TN | 功能描述:網(wǎng)絡(luò)控制器與處理器 IC 3.3V DS3/E3/STS-1 Line Interface Unit RoHS:否 制造商:Micrel 產(chǎn)品:Controller Area Network (CAN) 收發(fā)器數(shù)量: 數(shù)據(jù)速率: 電源電流（最大值）:595 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:PBGA-400 封裝:Tray |
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