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參數(shù)資料
| 型號： | DS3134 |
| 廠商： | DALLAS SEMICONDUCTOR |
| 元件分類： | Digital Transmission Controller |
| 英文描述： | DATACOM, FRAMER, PBGA256 |
| 封裝： | 27 X 27 MM, PLASTIC, BGA-256 |
| 文件頁數(shù)： | 191/203頁 |
| 文件大小： | 777K |
| 代理商： | DS3134 |
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DS3134
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Receive High Water Mark
The High Water Mark indicates to the device how many Blocks should be written into the receive FIFO
by the HDLC engines before the DMA will begin sending the data to the PCI Bus. Alternatively, in other
words, how full should the FIFO get before it should be emptied by the DMA. When the DMA begins
reading the data from the FIFO, it will read all available data and try to completely empty the FIFO even
if one or more EOF (End Of Frames) is detected. As an example, if four Blocks were link-listed together
and the Host programmed the High Water Mark to three Blocks, then the DMA would read the data out of
the FIFO and transfer it to the PCI Bus after the HDLC engine has written three complete Blocks in
succession into the FIFO and still had one Block left to fill. The DMA would not read the data out of the
FIFO again until another three complete Blocks had been written into the FIFO in succession by the
HDLC engine or until an EOF was detected. In this example of four Blocks being link-listed together, the
High Water Mark could also be set to 1 or 2 but no other values would be allowed. If an incoming packet
does not fill the FIFO enough to reach the High Water Mark before an EOF is detected, the DMA will
still request that the data be sent to the PCI Bus, it will not wait for additional data to be written into the
FIFO by the HDLC engines.
Transmit Low Water Mark
The Low Water Mark indicates to the device how many Blocks should be left in the FIFO before the
DMA should begin getting more data from the PCI Bus. In other words, how empty should the FIFO get
before it should be filled again by the DMA. When the DMA begins reading the data from the PCI Bus, it
will read all available data and try to completely fill the FIFO even if one or more EOF (i.e. HDLC
packets) is detected. As an example, if five Blocks were link-listed together and the Host programmed
the Low Water Mark to two Blocks, then the DMA would read the data from the PCI Bus and transfer it
to the FIFO after the HDLC engine has read three complete Blocks in succession from the FIFO and
hence still had two blocks left before the FIFO was empty. The DMA would not read the data from the
PCI Bus again until another three complete Blocks had been read from the FIFO in succession by the
HDLC engines. In this example of five Blocks being link-listed together, the Low Water Mark could also
be set to any value from 1 to 3 (inclusive) but no other values would be allowed. In another words the
Transmit Low Water Mark can be set to a value of 1 to N – 2, where N = number of blocks are linked
together. When a new packet is written into a completely empty FIFO by the DMA, the HDLC engines
will wait until the FIFO fills beyond the Low Water Mark or until an EOF is seen before reading the data
out of the FIFO.
7.2 FIFO REGISTER DESCRIPTION
Register Name:
RFSBPIS
Register Description: Receive FIFO Starting Block Pointer Indirect Select
Register Address:
0900h
76
5432
10
HCID7
HCID6
HCID5
HCID4
HCID3
HCID2
HCID1
HCID0
15
14
13
12
11
10
9
8
IAB
IARW
n/a
Note: Bits that are underlined are read only, all other bits are read-write; default value for all bits is 0.
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