- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄1915 > DS28CM00R-A00+T (Maxim Integrated Products)IC SILICON SERIAL NUMBER SOT23-5 PDF資料下載
參數(shù)資料
| 型號： | DS28CM00R-A00+T |
| 廠商： | Maxim Integrated Products |
| 文件頁數(shù)： | 6/9頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC SILICON SERIAL NUMBER SOT23-5 |
| 產(chǎn)品培訓(xùn)模塊： | Lead (SnPb) Finish for COTS Obsolescence Mitigation Program |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 類型： | 硅序列號 |
| 應(yīng)用： | PCB，網(wǎng)絡(luò)節(jié)點，設(shè)備識別/注冊 |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | SC-74A，SOT-753 |
| 供應(yīng)商設(shè)備封裝： | SOT-23-5 |
| 包裝： | 標(biāo)準(zhǔn)包裝 |
| 其它名稱： | DS28CM00R-A00+TDKR |
DS28CM00: IC/SMBus Silicon Serial Number
6 of 9
Figure 4. IC/SMBus Protocol Overview
SCL
SDA
12
6
7
8
ACK
9
12
8
MS-bit
R/W
Slave Address
ACK
bit
Acknowledgment
from Receiver
ACK
bit
START
Condition
ACK
Repeated if more bytes
are transferred
STOP Condition
Repeated START
Condition
Idle
Bus Idle or Not Busy
Both, SDA and SCL, are inactive, i. e., in their logic HIGH states.
START Condition
To initiate communication with a slave, the master has to generate a START condition. A START condition is
defined as a change in state of SDA from HIGH to LOW while SCL remains HIGH.
STOP Condition
To end communication with a slave, the master has to generate a STOP condition. A STOP condition is defined as
a change in state of SDA from LOW to HIGH while SCL remains HIGH.
Repeated START Condition
Repeated starts are commonly used for read accesses to select a specific data source or address to read from.
The master can use a repeated START condition at the end of a data transfer to immediately initiate a new data
transfer following the current one. A repeated START condition is generated the same way as a normal START
condition, but without leaving the bus idle after a STOP condition.
Data Valid
With the exception of the START and STOP condition, transitions of SDA may occur only during the LOW state of
SCL. The data on SDA must remain valid and unchanged during the entire high pulse of SCL plus the required
setup and hold time (tHD:DAT after the falling edge of SCL and tSU:DAT before the rising edge of SCL, see Figure 5).
There is one clock pulse per bit of data. Data is shifted into the receiving device during the rising edge of the SCL
pulse.
When finished with writing, the master must release the SDA line for a sufficient amount of setup time (minimum
tSU:DAT + tR in Figure 5) before the next rising edge of SCL to start reading. The slave shifts out each data bit on
SDA at the falling edge of the previous SCL pulse and the data bit is valid at the rising edge of the current SCL
pulse. The master generates all SCL clock pulses, including those needed to read from a slave.
Acknowledged
Usually, a receiving device, when addressed, is obliged to generate an acknowledge after the receipt of each byte.
The master must generate a clock pulse that is associated with this acknowledge bit. A device that acknowledges
must pull SDA LOW during the acknowledge clock pulse in such a way that SDA is stable LOW during the HIGH
period of the acknowledge-related clock pulse plus the required setup and hold time (tHD:DAT after the falling edge of
SCL and tSU:DAT before the rising edge of SCL).
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| DS30EA101SQE/NOPB | IC CABLE EQUALIZER 16LLP |
| DS3120N | IC FRAMER T1 28-CHANNEL IND |
| DS31256+ | IC CTRLR HDLC 256-CHANNEL 256BGA |
| DS3141+ | IC FRAMER DS3/E3 SNGL 144CSBGA |
| DS31412N | IC 12CH DS3/3 FRAMER 349-BGA |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| DS28CN01 | 制造商:MAXIM 制造商全稱:Maxim Integrated Products 功能描述:1Kbit IC/SMBus EEPROM with SHA-1 Engine |
| DS28CN01_09 | 制造商:MAXIM 制造商全稱:Maxim Integrated Products 功能描述:1Kb I2C/SMBus EEPROM with SHA-1 Engine |
| DS28CN01_0911 | 制造商:MAXIM 制造商全稱:Maxim Integrated Products 功能描述:1Kb I2C/SMBus EEPROM with SHA-1 Engine |
| DS28CN01EVKIT | 制造商:Maxim Integrated Products 功能描述:DS28CN01 EVAL BOARD KIT - Rail/Tube |
| DS28CN01U+ | 制造商:MAXIM 制造商全稱:Maxim Integrated Products 功能描述:1Kbit IC/SMBus EEPROM with SHA-1 Engine |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。