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參數(shù)資料
| 型號： | DS2890X-000 |
| 廠商： | Maxim Integrated Products |
| 文件頁數(shù)： | 20/27頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC POT DIGITAL 1-WIRE 100K CSP |
| 標準包裝： | 10,000 |
| 接片： | 256 |
| 電阻（歐姆）： | 100k |
| 電路數(shù)： | 1 |
| 溫度系數(shù)： | 標準值 800 ppm/°C |
| 存儲器類型： | 易失 |
| 接口： | 1 線 串行 |
| 電源電壓： | 2.8 V ~ 6 V |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 6-XBGA，F(xiàn)CBGA |
| 供應(yīng)商設(shè)備封裝： | 6-覆晶（2.82x2.54） |
| 包裝： | 帶卷 (TR) |
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DS2890
27 of 27
AC ELECTRICAL CHARACTERISTICS - OVERDRIVE 1-WIRE SPEED
2.8V
≤ V
PUP ≤ 6.0V, -40°C ≤ TA ≤ +85°C
PARAMETER
SYMBOL
MIN
TYP
MAX
UNITS
NOTES
Recovery Time
tREC
1
s
Reset High Time
tRSTH
48
s
Reset Low Time
tRSTL
48
80
s
Presence Detect High
tPDH
2
6
s
Presence Detect Low
tPDL
8
24
s
Notes:
1. The optimal sampling point for the master is as close as possible to the end time of the 2
μs t
RDV
period without exceeding tRDV. For the case of a Read-one time slot, this maximizes the amount of
time for the pull-up resistor to recover the line to a high level. For a Read-zero time slot it ensures
that a read will occur before the fastest 1-Wire device(s) release the line (tRELEASE = 0).
2. Read data setup time refers to the time the host must pull the 1-Wire bus low to read a bit. Data is
guaranteed to be valid within 1 s of this falling edge.
3. An additional reset or communication sequence cannot begin until the reset high time (tRSTH) has
expired.
4. The reset low time (tRSTL) should be restricted to a maximum of 960 s, to allow interrupt signaling,
otherwise, it could mask or conceal interrupt pulses.
CAPACITANCE
TA = 25
°C
PARAMETER
SYMBOL
MIN
TYP
MAX
UNITS
NOTES
1-Wire Pin
800
pF
1
VDD Pin
10
pF
Resistor Terminals
10
pF
NOTE:
1. Capacitance on the 1-Wire pin could be 800 pF when power is first applied. If a 5 k
Ω is used to pull
up the 1-Wire line to VPUP, the capacitance will not affect communications after a 5 μs charge time.
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