參數(shù)資料
型號(hào)： DS2720CU/T&R
廠商： MAXIM INTEGRATED PRODUCTS INC
元件分類： 電源管理
英文描述： 1-CHANNEL POWER SUPPLY SUPPORT CKT, PDSO8
封裝： MICRO, SOP-8
文件頁(yè)數(shù)： 20/21頁(yè)
文件大小： 264K
代理商： DS2720CU/T&R
DS2720
8 of 21
MEMORY
The DS27xx family of products is organized into a 256-byte linear address space with registers for
instrumentation, status, and control in the lower 32 bytes, with lockable EEPROM memory occupying
portions of the remaining address space. All EEPROM memory is general purpose except address 31h,
which should be written with the default values for the status register.
EEPROM memory is shadowed by RAM to eliminate programming delays between writes and to allow
the data to be verified by the host system before being copied to EEPROM. All reads and writes to/from
EEPROM memory in fact access the shadow RAM. In unlocked EEPROM blocks, the write data
command updates shadow RAM. In locked EEPROM blocks, the write data command is ignored. The
copy data command copies the contents of shadow RAM to EEPROM in an unlocked block of EEPROM
but has no effect on locked blocks. The recall data command copies the contents of a block of EEPROM
to shadow RAM regardless of whether the block is locked or not.
Table 4. MEMORY MAP
ADDRESS (hex)
DESCRIPTION
READ/WRITE
00
Protection Register
R/W
01
Status Register
R
02–06
Reserved
—
07
EEPROM Register
R
08
Special Feature Register
R/W
09–1F
Reserved
—
20–23
EEPROM, Block 0
R/W (1)
24–2F
Reserved
—
30–33
EEPROM, Block 1
(31 = Status Register Initialization)
R/W (1)
34–FF
Reserved
—
(1)
Each EEPROM block is read/write until locked by the LOCK command, after which it is read-only.
PROTECTION REGISTER
The protection register consists of flags that indicate protection circuit status and switches that give
conditional control over the charging and discharging paths. Bits OV, UV, and DOC are set when
corresponding protection conditions occur and remain set until cleared by the host system. The format of
the protection register is shown in Figure 4. The function of each bit is described in detail in the following
paragraphs.
Figure 4. PROTECTION REGISTER FORMAT
Address 00
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
OV
UV
0
DOC
CC
DC
CE
DE
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