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DS26528 Octal T1/E1/J1 Transceiver
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9.6
BERT Register Definitions
Table 9-21. BERT Register Set
ADDR
NAME
DESCRIPTION
R/W
1100h
BERT Alternating Word Count Rate Register
R
1101h
BERT Repetitive Pattern Set Register 1
R/W
1102h
BERT Repetitive Pattern Set Register 2
R/W
1103h
BERT Repetitive Pattern Set Register 3
R/W
1104h
BERT Repetitive Pattern Set Register 4
R/W
1105h
BERT Control Register 1
R/W
1106h
BERT Control Register 2
R/W
1107h
BERT Bit Count Register 1
R
1108h
BERT Bit Count Register 2
R
1109h
BERT Bit Count Register 3
R
110Ah
BERT Bit Count Register 4
R
110Bh
BERT Error Count Register 1
R
110Ch
BERT Error Count Register 2
R
110Dh
BERT Error Count Register 3
R
110Eh
BERT Latched Status Register
R
110Fh
BERT Status Interrupt Mask Register
R/W
Register Name:
BAWC
Register Description:
BERT Alternating Word Count Rate Register
Register Address:
1100h + (10h x n): where n = 0 to 7, for Ports 1 to 8
Bit #
7
6
5
4
3
2
1
0
Name
ACNT7
ACNT6
ACNT5
ACNT4
ACNT3
ACNT2
ACNT1
ACNT0
Default
0
Bits 7 to 0: Alternating Word Count Rate Bits 7 to 0 (ACNT[7:0]). When the BERT is programmed in the
alternating word mode, the words will repeat for the count loaded into this register, then flip to the other word and
again repeat for the number of times loaded into this register. ACNT0 is the LSB of the 8-bit alternating word count
rate counter.