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| 型號(hào)： | DS26401N+ |
| 廠商： | Maxim Integrated Products |
| 文件頁(yè)數(shù)： | 290/309頁(yè) |
| 文件大?。?/td> | 0K |
| 描述： | IC OCTAL FRAMER T1/E1/J1 256-BGA |
| 產(chǎn)品培訓(xùn)模塊： | Lead (SnPb) Finish for COTS Obsolescence Mitigation Program |
| 標(biāo)準(zhǔn)包裝： | 90 |
| 控制器類(lèi)型： | T1/E1/J1 調(diào)幀器 |
| 接口： | WAN |
| 電源電壓： | 3.135 V ~ 3.465 V |
| 電流 - 電源： | 275mA |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類(lèi)型： | 表面貼裝 |
| 封裝/外殼： | 256-LBGA，CSBGA |
| 供應(yīng)商設(shè)備封裝： | 256-CSBGA（17x17） |
| 包裝： | 托盤(pán) |
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DS26401 Octal T1/E1/J1 Framer
81
8.14.2 Additional Receive-Elastic-Store Information
If the receive-side elastic store is enabled, then the user must provide either a 1.544MHz or 2.048MHz clock at the
RSYSCLK pin. For higher rate system clock applications, see the Interleaved PCM Bus Option in Section 8.21. The
user has the option of either providing a frame/multiframe sync at the RSYNC pin or having the RSYNC pin provide
a pulse on frame/multiframe boundaries. If signaling reinsertion is enabled, the robbed-bit signaling data is
realigned to the multiframe-sync input on RSYNC. Otherwise, a multiframe-sync input on RSYNC is treated as a
simple frame boundary by the elastic store. The framer always indicated frame boundaries on the network side of
the elastic store through the RFSYNC output, whether the elastic store is enabled or not. Multiframe boundaries are
always indicated through the RMSYNC output. If the elastic store is enabled, RMSYNC outputs the multiframe
boundary on the backplane side of the elastic store. When the device is receiving T1, and the backplane is enabled
for 2.048MHz operation, the RMSYNC signal outputs the T1 multiframe boundaries as delayed through the elastic
store.
If the user selects to apply a 2.048MHz clock to the RSYSCLK pin, then the backplane blank-channel-select
registers (RBCS1–4) can be used to determine which channels have the data output at RSER forced to all ones. If
the user chooses to blank time slot 0, then the F-bit is passed into the MSB of TS0. If the two-frame elastic buffer
either fills or empties, a controlled slip occurs. If the buffer empties, a full frame of data is repeated at RSER, and
the RLS4.5 and RLS4.6 bits are set to 1. If the buffer fills, a full frame of data is deleted, and the RLS4.5 and
RLS4.7 bits are set to 1.
8.14.2.1 Elastic Store Initialization
There are two elastic-store initializations that can be used to improve performance in certain applications—the
elastic-store reset and elastic-store align. Both of these involve the manipulation of the elastic store’s read and write
pointers, and are useful primarily in synchronous applications (RSYSCLK/TSYSCLK are locked to RCLK/TCLK
respectively). The elastic-store reset is used to minimize the delay through the elastic store. The elastic-store align
bit is used to center the read/write pointers to the extent possible.
Elastic Store Delay After Initialization
INITIALIZATION
REGISTER BIT
DELAY
Receive-Elastic-Store Reset
RESCR.2
N bytes < Delay < 1 Frame + N bytes
Transmit-Elastic-Store Reset
TESCR.2
N bytes < Delay < 1 Frame + N bytes
Receive-Elastic-Store Align
RESCR.3
1/2 Frame < Delay < 1 Frames
Transmit-Elastic-Store Align
TESCR.3
1/2 Frame < Delay < 1 Frames
N = 9 for RSZS = 0
N = 2 for RSZS = 1
8.14.2.2 Minimum-Delay Mode
Elastic-store minimum-delay mode can be used when the elastic store’s system clock is locked to its network clock
(i.e., RCLK locked to RSYSCLK for the receive side and TCLK locked to TSYSCLK for the transmit side). RESCR.1
enables the receive-elastic-store minimum-delay mode. When enabled, the elastic stores are forced to a maximum
depth of 32 bits instead of the normal two-frame depth. This feature is useful primarily in applications that interface
to a 2.048MHz bus. Certain restrictions apply when minimum-delay mode is used. In addition to the restriction
mentioned above, RSYNC must be configured as an output when the receive-elastic store is in minimum-delay
mode and TSYNC must be configured as an output when transmit-minimum-delay mode is enabled. In a typical
application, RSYSCLK and TSYSCLK are locked to RCLK, and RSYNC (frame-output mode) is connected to
TSSYNC (frame-input mode). All the slip contention logic in the framer is disabled (since slips cannot occur). On
power-up, after the RSYSCLK and TSYSCLK signals have locked to their respective network clock signals, the
elastic-store-reset bit (RESCR.2) should be toggled from zero to 1 to ensure proper operation.
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| DS26401N+ | 功能描述:網(wǎng)絡(luò)控制器與處理器 IC Octal T1/E1/J1 Framer RoHS:否 制造商:Micrel 產(chǎn)品:Controller Area Network (CAN) 收發(fā)器數(shù)量: 數(shù)據(jù)速率: 電源電流（最大值）:595 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:PBGA-400 封裝:Tray |
| DS26401NA2 | 功能描述:網(wǎng)絡(luò)控制器與處理器 IC Octal T1/E1/J1 Framer RoHS:否 制造商:Micrel 產(chǎn)品:Controller Area Network (CAN) 收發(fā)器數(shù)量: 數(shù)據(jù)速率: 電源電流（最大值）:595 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:PBGA-400 封裝:Tray |
| DS26401NA2+ | 功能描述:網(wǎng)絡(luò)控制器與處理器 IC Octal T1/E1/J1 Framer RoHS:否 制造商:Micrel 產(chǎn)品:Controller Area Network (CAN) 收發(fā)器數(shù)量: 數(shù)據(jù)速率: 電源電流（最大值）:595 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:PBGA-400 封裝:Tray |
| DS26502 | 制造商:MAXIM 制造商全稱(chēng):Maxim Integrated Products 功能描述:T1/E1/J1/64KCC BITS Element |
| DS26502_06 | 制造商:DALLAS 制造商全稱(chēng):Dallas Semiconductor 功能描述:T1/E1/J1/64KCC BITS Element |
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