參數(shù)資料
型號(hào): DS26334GNA3+
廠商: Maxim Integrated Products
文件頁數(shù): 46/121頁
文件大?。?/td> 0K
描述: IC LIU E1/T1/J1 3.3V 256-CSBGA
產(chǎn)品培訓(xùn)模塊: Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
標(biāo)準(zhǔn)包裝: 90
類型: 線路接口裝置(LIU)
驅(qū)動(dòng)器/接收器數(shù): 16/16
規(guī)程: IEEE 1149.1
電源電壓: 3.135 V ~ 3.465 V
安裝類型: 表面貼裝
封裝/外殼: 256-LBGA,CSBGA
供應(yīng)商設(shè)備封裝: 256-CSBGA(17x17)
包裝: 托盤
DS26334 3.3V, 16-Channel, E1/T1/J1 Short/Long-Haul Line Interface Unit
30 of 121
Table 5-10. Registers Related to AIS Detection
REGISTER
NAME
FUNCTIONALITY
LOS/AIS Criteria Selection
Section criteria for AIS (T1.231, G.775, ETS 300 233 for E1).
Alarm Indication Signal Status
Set when AIS is detected.
AIS Interrupt Enable
If reset, interrupt due to AIS is not generated.
AIS Interrupt Status
Latched if there is a change in AIS and the interrupt is enabled.
5.5.8
Receive Dual-Rail Mode
Receive dual-rail mode consists of the RPOS, RNEG, and RCLK pins on the system side. In receive dual-rail
mode, B8ZS and HDB3 decoding is not available. The data that appears on the RTIP and RRING pins is output on
RPOS and RNEG without any modification. The Single-Rail Mode Select Register (SRMS) is used for selection of
dual-rail or single-rail mode. The bipolar violation (and B8ZS/HDB3) detectors detect violations in dual-rail and
single-rail modes, but in dual-rail mode the violations will only be reported to the Line Violation Detect Status
(LVDS) registers.
5.5.9
Receive Single-Rail Mode
Receive single-rail mode consists of the RPOS, RCLK, and CV pins on the system side. B8ZS or HDB3 decoding
is available. The Single-Rail Mode Select Register (SRMS) is used for selection of dual-rail or single-rail mode.
5.5.10 Bipolar Violation and Excessive Zero Detector
The DS26334 detects HDB3 code violations, BPVs, and excessive zero errors. The reporting of the errors is done
through the RNEGn/CVn pin in single-rail mode and the LVDS registers in both single- and dual-rail modes. Code
violations are only detected in E1 mode with HDB3 encoding. The code violation detection declares an error when
a bipolar violation of the same polarity as the last bipolar violation is received.
Excessive zeros are detected if eight consecutive zeros are detected with B8ZS enabled and four consecutive
zeros are detected with HDB3 enabled. Excessive zero detection is enabled via the Excessive Zero Detect Enable
Register (EZDE) and when HDB3/B8ZS encoding/decoding is selected via the Line Code Selection Register (LCS).
The bits in the LCS, EZDE, and CVDEB registers determine the combinations that are reported. Table 5-11
outlines the functionality.
Table 5-11. BPV, Code Violation, and Excessive Zero Error Reporting
CONDITIONS
ERRORS DETECTED
0
BPV (T1)/Code Violation (E1)
0
1
BPV
0
1
0
Excessive Zeros and BPV (T1)/Code Violation (E1)
0
1
Excessive Zeros and BPV
1
X
BPV
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