
DS2482-101
Single-Channel 1-Wire Master with Sleep Mode
4
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Note 1:
Operating current with 1-Wire write-byte sequence followed by continuously reading the Status Register at 400kHz in overdrive.
Note 2:
With standard speed, the total capacitive load of the 1-Wire bus should not exceed 1nF. Otherwise, the passive pullup on
threshold VIL1 may not be reached in the available time. With overdrive speed, the capacitive load on the 1-Wire bus must
not exceed 300pF.
Note 3:
Active pullup guaranteed to turn on between VIL1(MAX) and VIH1(MIN).
Note 4:
Active or resistive pullup choice is configurable.
Note 5:
Except for tF1, all 1-Wire timing specifications and tAPUOT are derived from the same timing circuit. Therefore, if one of
these parameters is found to be off the typical value, it is safe to assume that all these parameters deviate from their typi-
cal value in the same direction and by the same degree.
Note 6:
These values apply at full load, i.e., 1nF at standard speed and 0.3nF at overdrive speed. For reduced load, the pulldown
slew rate is slightly faster.
Note 7:
Fall time high-to-low (tF1) is derived from PDSRC, referenced from 0.9 x VCC to 0.1 x VCC.
Note 8:
I2C communication should not take place for the max tOSCWUP or tSWUP time following a power-on reset or a wakeup from
sleep mode.
Note 9:
Guaranteed by design and not production tested.
Note 10: All I2C timing values are referred to VIH(MIN) and VIL(MAX) levels.
Note 11: Applies to SDA, SCL, and AD0.
Note 12: The input/output pins of the DS2482-101 do not obstruct the SDA and SCL lines if VCC is switched off.
Note 13: The DS2482-101 provides a hold time of at least 300ns for the SDA signal (referred to the VIH(MIN) of the SCL signal) to
bridge the undefined region of the falling edge of SCL.
Note 14: The maximum tHD:DAT need only be met if the device does not stretch the low period (tLOW) of the SCL signal.
Note 15: A fast-mode I2C bus device can be used in a standard-mode I2C bus system, but the requirement tSU:DAT
≥ 250ns must
then be met. This is automatically the case if the device does not stretch the low period of the SCL signal. If such a device
does stretch the low period of the SCL signal, it must output the next data bit to the SDA line tR(MAX) + tSU:DAT = 1000 +
250 = 1250ns (according to the standard-mode I2C bus specification) before the SCL line is released.
Note 16: CB—Total capacitance of one bus line in pF. If mixed with high-speed-mode devices, faster fall times according to I2C-
Bus Specification Version 2.1 are allowed.
ELECTRICAL CHARACTERISTICS (continued)
(VCC = 2.9V to 5.5V, TA = -40°C to +85°C.)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
Input Current Each Input/Output
Pin with an Input Voltage
Between 0.1 x VCC(MAX) and
0.9 x VCC(MAX)
II
(Notes 11, 12)
-10
+10
μA
Input Capacitance
CI
(Note 11)
10
pF
SCL Clock Frequency
fSCL
0
400
kHz
Hold Time (Repeated) START
Condition (After this period, the
first clock pulse is generated.)
tHD:STA
0.6
μs
Low Period of the SCL Clock
tLOW
1.3
μs
High Period of the SCL Clock
tHIGH
0.6
μs
Setup Time for a Repeated
START Condition
tSU:STA
0.6
μs
Data Hold Time
tHD:DAT
(Notes 13, 14)
0.9
μs
Data Setup Time
tSU:DAT
(Note 15)
250
ns
Setup Time for STOP Condition
tSU:STO
0.6
μs
Bus Free Time Between a STOP
and START Condition
tBUF
1.3
μs
Capacitive Load for Each Bus
Line
CB
(Note 16)
400
pF
Oscillator Warmup Time
tOSCWUP
(Note 8)
100
μs