tSLOT Standard speed 65 s
參數(shù)資料
型號: DS2411P+T&R
廠商: Maxim Integrated Products
文件頁數(shù): 6/12頁
文件大小: 0K
描述: IC SILICON SERIAL NUMBER 6TSOC
產(chǎn)品培訓模塊: Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
標準包裝: 4,000
類型: 硅序列號
應用: PCB,網(wǎng)絡節(jié)點,設備識別/注冊
安裝類型: 表面貼裝
封裝/外殼: 6-LSOJ
供應商設備封裝: 6-TSOC
包裝: 帶卷 (TR)
DS2411
3 of 12
PARAMETER
SYMBOL
CONDITIONS
MIN MAX UNITS
Timeslot Duration
tSLOT
Standard speed
65
s
Overdrive VCC ≥ 2.2V
8
Overdrive VCC ≥ 1.5V
10
I/O PIN, 1-Wire RESET, PRESENCE DETECT CYCLE
Reset Low Time
tRSTL
Standard speed
480
640
s
Overdrive speed
60
80
Presence-Detect High Time
tPDH
Standard speed
15
60
s
Overdrive VCC ≥ 2.2V
2
6
Overdrive VCC ≥ 1.5V
2
8.5
Presence-Detect Low Time
tPDL
Standard speed
60
240
s
Overdrive VCC ≥ 2.2V
8
24
Overdrive VCC ≥ 1.5V
8
30
Presence-Detect Fall Time
tFPD
Standard speed (Note 10, 3)
0.4
8
s
Overdrive speed (Note 10, 3)
0.05
1
Presence-Detect Sample
Time
tMSP
Standard speed (Note 1)
60
75
s
Overdrive VCC ≥ 2.2V (Note 1)
6
10
Overdrive VCC ≥ 1.5V (Note 1)
8.5
10
I/O PIN, 1-Wire WRITE
Write-0 Low Time
tW0L
Standard speed (Notes 1, 11, 13)
60
120
s
Overdrive VCC ≥ 2.2V
(Notes 1, 11, 13)
6
16
Overdrive VCC ≥ 1.5V
(Notes 1, 11, 13)
8
16
Write-1 Low Time
tW1L
Standard speed (Notes 1, 11, 13)
5
15
s
Overdrive speed (Notes 1, 11, 13)
1
2
I/O PIN, 1-Wire READ
Read Low Time
tRL
Standard speed (Notes 1, 12)
5
15 - δ
s
Overdrive speed (Notes 1, 12)
1
2 - δ
Read Sample Time
tMSR
Standard speed (Notes 1, 12)
tRL + δ
15
s
Overdrive speed (Notes 1, 12)
tRL + δ
2
Note 1:
System requirement.
Note 2:
Maximum allowable pullup resistance is a function of the number of 1-Wire devices in the
system and 1-Wire recovery times. The specified value here applies to systems with only
one device and with the minimum 1-Wire recovery times. For more heavily loaded
systems, an active pullup such as that found in the DS2480B may be required. Minimum
allowable pullup resistance is slightly greater than the value necessary to produce the
absolute maximum current (20mA) during 1-Wire low times at VPUP = 5.25V assuming
VOL = 0V.
Note 3:
Not production tested.
Note 4:
VTL and VTH are functions of VCC and temperature. The VTH and VTL maximum specifica-
tions are valid at VCC = 5.25V. In any case, VTL < VTH < VCC.
Note 5:
Voltage below which during a falling edge on I/O, a logic ‘0’ is detected.
Note 6:
Voltage above which during a rising edge on I/O, a logic ‘1’ is detected.
Note 7:
After VTH is crossed during a rising edge on I/O, the voltage on I/O has to drop by VHY to
be detected as logic ‘0’.
Note 8:
The I-V characteristic is linear for voltages less than 1V.
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