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參數(shù)資料
| 型號： | DS2408S+T&R |
| 廠商： | Maxim Integrated Products |
| 文件頁數(shù)： | 18/39頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC SWITCH 8-CHAN ADDRESS 16SOIC |
| 標準包裝： | 2,500 |
| 接口： | 1 線 |
| 輸入/輸出數(shù)： | 8 |
| 中斷輸出： | * |
| 電源電壓： | 2.8 V ~ 5.25 V |
| 工作溫度： | * |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 16-SOIC（0.154"，3.90mm 寬） |
| 供應商設(shè)備封裝： | 16-SOIC |
| 包裝： | 帶卷 (TR) |
| 包括： | * |
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DS2408
25 of 39
Read/Write Time Slots
Data communication with the DS2408 takes place in time slots, which carry a single bit each. Write time
slots transport data from bus master to slave. Read time slots transfer data from slave to master. The
definitions of the write and read time slots are illustrated in Figure 14.
All communication begins with the master pulling the data line low. As the voltage on the 1-Wire line
falls below the threshold VTL, the DS2408 starts its internal time base. The tolerance of the slave time
base creates a slave-sampling window, which stretches from tSLSMIN to tSLSMAX. The voltage on the data
line at the sampling point determines whether the DS2408 decodes the time slot as 1 or 0.
Master-to-Slave
For a write-one time slot, the voltage on the data line must have crossed the VTHMAX threshold after the
write-one low time tW1LMAX has expired. For a write-zero time slot, the voltage on the data line must stay
below the VTHMIN threshold until the write-zero low time tW0LMIN has expired. For most reliable
communication, the voltage on the data line should not exceed VILMAX during the entire tW0L window.
After the VTHMAX threshold has been crossed, the DS2408 needs a recovery time tREC before it is ready for
the next time slot.
Figure 14. READ/WRITE TIMING DIAGRAM
Write-One Time Slot
VPUP
VIHMASTER
VTH
VTL
VILMAX
0V
DS2408
Sampling
Window
tSLSMIN
tF
tSLOT
tW1L
tSLSMAX
ε
Write-Zero Time Slot
tREC
VPUP
VIHMASTER
VTH
VTL
VILMAX
0V
DS2408
Sampling
Window
tSLSMIN
tF
tSLOT
tSLSMAX
tW0L
ε
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