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參數(shù)資料
| 型號： | DS2405+ |
| 廠商： | Maxim Integrated Products |
| 文件頁數(shù)： | 7/15頁 |
| 文件大小： | 0K |
| 描述： | IC SWITCH ADDRESS NCH O-D TO-92 |
| 產(chǎn)品培訓模塊： | Lead (SnPb) Finish for COTS Obsolescence Mitigation Program |
| 標準包裝： | 1 |
| 接口： | 1 線 |
| 電源電壓： | 2.8 V ~ 6 V |
| 封裝/外殼： | TO-226-3、TO-92-3 標準主體 |
| 供應(yīng)商設(shè)備封裝： | TO-92-3 |
| 包裝： | 管件 |
| 安裝類型： | 通孔 |
DS2405
15 of 15
NOTES:
1. All voltages are referenced to ground.
2. VPUP = external pullup voltage.
3. Input load is to ground.
4. An additional reset or communication sequence cannot begin until the reset high time has expired.
5. Read data setup time refers to the time the host must pull the 1-Wire bus low to read a bit. Data is
guaranteed to be valid within 1
μs of this falling edge and will remain valid for 14μs minimum (15μs
total from falling edge on 1-Wire bus).
6. VIH is a function of the external pull-up resistor and the VCC supply.
7. Capacitance on the data pin could be 800pF when power is first applied. If a 5k
Ω resistor is used to
pull-up the data line to VCC, 5μs after power has been applied the parasite capacitance will not affect
normal communications.
8. VIH for PIO pin should always be greater than or equal to VPUP -0.3V.
9. Input resistance is to ground.
10. Under certain low voltage conditions VILMAX may have to be reduced to as much as 0.5V to always
guarantee a Presence Pulse.
11. The optimal sampling point for the master is as close as possible to the end of the 15μs tRDV period
without exceeding tRDV. For the case of a Read 1 time slot, this maximizes the amount of time for the
pull-up resistor to recover the line to a high level. For a Read 0 time slot, it ensures that a read will
occur before the fastest 1-Wire device(s) release the line.
12. The duration of the low pulse sent by the master should be a minimum of 1μs with a maximum value
as short as possible to allow time for the pull-up resistor to recover the line to a high level before the
1-Wire device samples in the case of a Write 1 Low Time, or before the master samples in the case of
a Read Low Time.
13. The Reset Low Time (tRSTL) should be restricted to a maximum of 960μs to allow interrupt signaling;
otherwise, it could mask or conceal interrupt pulses.
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