參數(shù)資料
型號(hào): DS21Q50LN
廠商: Maxim Integrated Products
文件頁(yè)數(shù): 21/87頁(yè)
文件大?。?/td> 0K
描述: IC TRANSCEIVER E1 QD IND 100LQFP
產(chǎn)品培訓(xùn)模塊: Lead (SnPb) Finish for COTS
產(chǎn)品變化通告: Product Discontinuation 20/Feb/2012
標(biāo)準(zhǔn)包裝: 90
功能: 收發(fā)器
接口: E1
電路數(shù): 4
電源電壓: 3.14 V ~ 3.47 V
電流 - 電源: 230mA
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 100-LQFP
供應(yīng)商設(shè)備封裝: 100-LQFP(14x14)
包裝: 托盤(pán)
包括: AIS 警報(bào)檢測(cè)器和發(fā)生器,回送功能,PRBS 發(fā)生器 / 檢測(cè)器,遠(yuǎn)程檢測(cè)器和發(fā)生器
DS21Q50
28 of 87
4.2 Framer Loopback
When CCR1.7 is set to 1, the DS21Q50 enters a framer loopback (FLB) mode (Figure 1-1). This
loopback is useful in testing and debugging applications. In FLB, the SCT loops data from the transmitter
back to the receiver. When FLB is enabled, the following occurs:
1) Data is transmitted as normal at TTIP and TRING.
2) The RCLK output is replaced with the TCLK input.
Register Name:
CCR2
Register Description:
Common Control Register 2
Register Address:
13 Hex
Bit
7
6
5
4
3
2
1
0
Name
RCUS
VCRFS
AAIS
ARA
RSERC
LOTCMC
RCLA
TCSS
SYMBOL
BIT
FUNCTION
ECUS
7
Error Counter Update Select. See Section 6 for details.
0 = update error counters once a second
1 = update error counters every 62.5ms (500 frames)
VCRFS
6
VCR Function Select. See Section 6 for details.
0 = count bipolar violations (BPVs)
1 = count code violations (CVs)
AAIS
5
Automatic AIS Generation
0 = disabled
1 = enabled
ARA
4
Automatic Remote Alarm Generation
0 = disabled
1 = enabled
RSERC
3
RSER Control
0 = allow RSER to output data as received under all conditions
1 = force RSER to one under loss-of-frame alignment conditions
LOTCMC
2
Loss-of-Transmit Clock Mux Control. Determines whether the transmit formatter should
switch to the ever present RCLK if the TCLK should fail to transition (Figure 1-1).
0 = do not switch to RCLK if TCLK stops
1 = switch to RCLK if TCLK stops
RCLA
1
Receive Carrier Loss (RCL) Alternate Criteria
0 = RCL declared upon 255 consecutive 0s (125
ms)
1 = RCL declared upon 2048 consecutive 0s (1ms)
TCSS
0
Transmit Clock Source Select. This function allows the user to internally select RCLK as
the clock source for the transmit formatter.
0 = source of transmit clock determined by CCR2.2 (LOTCMC)
1 = force transmitter to internally switch to RCLK as source of transmit clock. Signal at
TCLK pin is ignored
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