- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄9750 > DS21Q48A3N (Maxim Integrated Products)IC LIU 5V E1/T1/J1 144-BGA PDF資料下載
參數(shù)資料
| 型號： | DS21Q48A3N |
| 廠商： | Maxim Integrated Products |
| 文件頁數(shù)： | 28/73頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC LIU 5V E1/T1/J1 144-BGA |
| 產(chǎn)品培訓模塊： | Lead (SnPb) Finish for COTS Obsolescence Mitigation Program |
| 標準包裝： | 1 |
| 類型： | 線路接口裝置（LIU） |
| 規(guī)程： | E1 |
| 電源電壓： | 4.75 V ~ 5.25 V |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 144-BBGA |
| 供應商設備封裝： | 144-PBGA（17x17） |
| 包裝： | 管件 |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁當前第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁第42頁第43頁第44頁第45頁第46頁第47頁第48頁第49頁第50頁第51頁第52頁第53頁第54頁第55頁第56頁第57頁第58頁第59頁第60頁第61頁第62頁第63頁第64頁第65頁第66頁第67頁第68頁第69頁第70頁第71頁第72頁第73頁
DS2148/DS21Q48
34 of 73
SYMBOL
POSITION
DESCRIPTION
RJAB
CCR6.3
RCLK Jitter Attenuator Bypass. This control bit allows the recovered
received clock and data to bypass the jitter attenuation while still
allowing the BPCLK output to use the jitter attenuator. See Figure 1-1
and Section 7.1 for details.
0 = disabled
1 = enabled
ECRS2
CCR6.2
Error Count Register Select 2. See Section 6.4 for details.
ECRS1
CCR6.1
Error Count Register Select 1. See Section 6.4 for details.
ECRS0
CCR6.0
Error Count Register Select 0. See Section 6.4 for details.
5 STATUS REGISTERS
There are three registers that contain information on the current real-time status of the device, status
register (SR), and receive information registers 1 and 2 (RIR1/RIR2). When a particular event has
occurred (or is occurring), the appropriate bit in one of these three registers will be set to a one. Some of
the bits in SR, RIR1, and RIR2 are latched bits and some are real-time bits. The register descriptions
below list which status bits are latched and which are real-time bits. For latched status bits, when an event
or an alarm occurs the bit is set to a one and will remain set until the user reads that bit. The bit will be
cleared when it is read and it will not be set again until the event has occurred again. Two of the latched
status bits (RUA1 & RCL) will remain set after reading if the alarm is still present.
The user will always precede a read of any of the three status registers with a write. The byte written to
the register will inform the DS2148 which bits the user wishes to read and have cleared. The user will
write a byte to one of these registers with a one in the bit positions to be read and a zero in the other bit
positions. When a one is written to a bit location, that location will be updated with the latest information.
When a zero is written to a bit position, that bit position will not be updated and the previous value will
be held. A write to the status and information registers will be immediately followed by a read of the
same register. The read result should be logically ANDed with the mask byte that was just written and
this value should be written back into the same register to ensure that bit does indeed clear. This second
write step is necessary because the alarms and events in the status registers occur asynchronously with
respect to their access via the parallel port. This write-read-write scheme allows an external
microcontroller or microprocessor to individually poll certain bits without disturbing the other bits in the
register. This operation is key in controlling the DS2148 with higher-order software languages.
The bits in the SR register have the unique ability to initiate a hardware interrupt via the
INT output pin.
Each of the alarms and events in the SR can be either masked or unmasked from the interrupt pin via the
interrupt mask register (IMR). The interrupts caused by the RCL, RUA1, and LOTC bits in SR act
differently than the interrupts caused by the other status bits in SR. The RCL, RUA1 and LOTC bits will
force the
INT pin low whenever they change state (i.e., go active or inactive). The INT pin will be
allowed to return high (if no other interrupts are present) when the user reads the alarm bit that caused the
interrupt to occur even if the alarm is still present. The other status bits in SR can force the
INT pin low
when they are set. The
INT pin will be allowed to return high (if no other interrupts are present) when the
user reads the event bit that caused the interrupt to occur.
相關PDF資料 |
PDF描述 |
|---|---|
| MC100EP17MNG | IC RCVR/DRVR QUAD DIFF ECL 20QFN |
| VI-26D-IU-F4 | CONVERTER MOD DC/DC 85V 200W |
| MS3102E12S-1S | CONN RCPT 2POS BOX MNT W/SCKT |
| VI-26D-IU-F2 | CONVERTER MOD DC/DC 85V 200W |
| MAX1239LEEE+ | IC ADC 12BIT SERIAL 16-QSOP |
相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| DS21Q48B | 功能描述:網(wǎng)絡控制器與處理器 IC RoHS:否 制造商:Micrel 產(chǎn)品:Controller Area Network (CAN) 收發(fā)器數(shù)量: 數(shù)據(jù)速率: 電源電流（最大值）:595 mA 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:PBGA-400 封裝:Tray |
| DS21Q48C | 功能描述:網(wǎng)絡控制器與處理器 IC RoHS:否 制造商:Micrel 產(chǎn)品:Controller Area Network (CAN) 收發(fā)器數(shù)量: 數(shù)據(jù)速率: 電源電流（最大值）:595 mA 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:PBGA-400 封裝:Tray |
| DS21Q48N | 功能描述:網(wǎng)絡控制器與處理器 IC 5V Quad E1/T1/J1 Line Interface RoHS:否 制造商:Micrel 產(chǎn)品:Controller Area Network (CAN) 收發(fā)器數(shù)量: 數(shù)據(jù)速率: 電源電流（最大值）:595 mA 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:PBGA-400 封裝:Tray |
| DS21Q48NB | 功能描述:網(wǎng)絡控制器與處理器 IC RoHS:否 制造商:Micrel 產(chǎn)品:Controller Area Network (CAN) 收發(fā)器數(shù)量: 數(shù)據(jù)速率: 電源電流（最大值）:595 mA 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:PBGA-400 封裝:Tray |
| DS21Q50 | 制造商:MAXIM 制造商全稱:Maxim Integrated Products 功能描述:Quad E1 Transceiver |
發(fā)布緊急采購，3分鐘左右您將得到回復。