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參數(shù)資料
| 型號(hào)： | DS21Q44T |
| 廠商： | MAXIM INTEGRATED PRODUCTS INC |
| 元件分類： | Digital Transmission Controller |
| 英文描述： | DATACOM, FRAMER, PQFP128 |
| 封裝： | TQFP-128 |
| 文件頁(yè)數(shù)： | 24/105頁(yè) |
| 文件大?。?/td> | 702K |
| 代理商： | DS21Q44T |
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DS21Q44
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ADDRESS
R/W
REGISTER NAME
REGISTER
ABBREVIATION
B1
R/W
HDLC Status Register
HSR
B2
R/W
HDLC Interrupt Mask Register
HIMR
B3
R/W
Receive HDLC Information Register
RHIR
B4
R/W
Receive HDLC FIFO Register
RHFR
B5
R/W
Interleave Bus Operation Register
IBO
B6
R/W
Transmit HDLC Information Register
THIR
B7
R/W
Transmit HDLC FIFO Register
THFR
B8
R/W
Receive HDLC DS0 Control Register 1
RDC1
B9
R/W
Receive HDLC DS0 Control Register 2
RDC2
BA
R/W
Transmit HDLC DS0 Control Register 1
TDC1
BB
R/W
Transmit HDLC DS0 Control Register 2
TDC2
BC
–
Not used
(set to 00H)
BD
–
Not used
(set to 00H)
BE
–
Not used
(set to 00H)
BF
–
Not used
(set to 00H)
NOTES:
1) Test Registers 1, 2, and 3 are used only by the factory; these registers must be cleared (set to all 0’s)
on power-up initialization to ensure proper operation.
2) Register banks CxH, DxH, ExH, and FxH are not accessible.
5. PARALLEL PORT
The DS21Q44 is controlled via either a non–multiplexed (MUX = 0) or a multiplexed (MUX = 1) bus by
an external microcontroller or microprocessor. The DS21Q44 can operate with either Intel or Motorola
bus timing configurations. If the BTS pin is tied low, Intel timing will be selected; if tied high, Motorola
timing will be selected. All Motorola bus signals are listed in parenthesis (). See the timing diagrams in
the A.C. Electrical Characteristics in Section 19 for more details.
6. CONTROL, ID, AND TEST REGISTERS
The operation of each framer within the DS21Q44 is configured via a set of ten control registers.
Typically, the control registers are only accessed when the system is first powered up. Once a channel in
the DS21Q44 has been initialized, the control registers will only need to be accessed when there is a
change in the system configuration. There are two Receive Control Register (RCR1 and RCR2), two
Transmit Control Registers (TCR1 and TCR2), and six Common Control Registers (CCR1 to CCR6).
Each of the ten registers are described in this section.
There is a device Identification Register (IDR) at address 0Fh. The MSB of this read–only register is
fixed to a one indicating that the DS21Q44 is present. The T1 pin–for–pin compatible version of the
DS21Q44 is the DS21Q42 and it also has an ID register at address 0Fh and the user can read the MSB to
determine which chip is present since in the DS21Q42 the MSB will be set to a zero and in the DS21Q44
it will be set to a one. The lower 4 bits of the IDR are used to display the die revision of the chip.
相關(guān)PDF資料 |
PDF描述 |
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| DS21Q48 | DATACOM, PCM TRANSCEIVER, PBGA144 |
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相關(guān)代理商/技術(shù)參數(shù) |
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| DS21Q44T+ | 功能描述:網(wǎng)絡(luò)控制器與處理器 IC Enhanced Quad E1 Framer RoHS:否 制造商:Micrel 產(chǎn)品:Controller Area Network (CAN) 收發(fā)器數(shù)量: 數(shù)據(jù)速率: 電源電流（最大值）:595 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:PBGA-400 封裝:Tray |
| DS21Q44TN | 功能描述:網(wǎng)絡(luò)控制器與處理器 IC RoHS:否 制造商:Micrel 產(chǎn)品:Controller Area Network (CAN) 收發(fā)器數(shù)量: 數(shù)據(jù)速率: 電源電流（最大值）:595 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:PBGA-400 封裝:Tray |
| DS21Q48 | 功能描述:網(wǎng)絡(luò)控制器與處理器 IC 5V Quad E1/T1/J1 Line Interface RoHS:否 制造商:Micrel 產(chǎn)品:Controller Area Network (CAN) 收發(fā)器數(shù)量: 數(shù)據(jù)速率: 電源電流（最大值）:595 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:PBGA-400 封裝:Tray |
| DS21Q48A3N | 功能描述:網(wǎng)絡(luò)控制器與處理器 IC 5V Quad E1/T1/J1 Line Interface RoHS:否 制造商:Micrel 產(chǎn)品:Controller Area Network (CAN) 收發(fā)器數(shù)量: 數(shù)據(jù)速率: 電源電流（最大值）:595 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:PBGA-400 封裝:Tray |
| DS21Q48B | 功能描述:網(wǎng)絡(luò)控制器與處理器 IC RoHS:否 制造商:Micrel 產(chǎn)品:Controller Area Network (CAN) 收發(fā)器數(shù)量: 數(shù)據(jù)速率: 電源電流（最大值）:595 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:PBGA-400 封裝:Tray |
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