參數(shù)資料
型號(hào)： DS21Q43AT
廠商： DALLAS SEMICONDUCTOR
元件分類： Digital Transmission Controller
英文描述： DATACOM, FRAMER, PQFP128
封裝： TQFP-128
文件頁數(shù)： 8/60頁
文件大?。?/td> 748K
代理商： DS21Q43AT
DS21Q43A
16 of 60
SYNC/RESYNC CRITERIA Table 3-1
FRAME OR MULTI-
FRAME LEVEL
SYNC CRITERIA
RESYNC CRITERIA
ITU SPEC.
FAS
FAS present in frame N
and N+2, and FAS not
present in frame N + 1
Three consecutive
incorrect FAS received
Alternate (RCR1.2=1)
the above criteria is
met or three
consecutive incorrect
bit 2 of non-FAS
received
G.706
4.1.1
4.1.2
CRC4
Two valid MF
alignment words found
within 8 ms
915 or more CRC4
code words out of 1000
received in error
G.706
4.2 and 4.3.2
CAS
Valid MF alignment
word found and
previous timeslot 16
contains code other
than all 0s
Two consecutive MF
alignment words
received in error
G.732
5.2
RCR2: RECEIVE CONTROL REGISTER 2 (Address=11 Hex)
(MSB)
(LSB)
Sa8S
Sa7S
Sa6S
Sa5S
Sa4S
RBCS
RESE
-
SYMBOL
POSITION
NAME AND DESCRIPTION
Sa8S
RCR2.7
Sa8 Bit Select. Set to 1 to report the Sa8 bit at the RLINK pin;
set to 0 to not report the Sa8 bit.
Sa7S
RCR2.6
Sa7 Bit Select. Set to 1 to report the Sa7 bit at the RLINK pin;
set to 0 to not report the Sa7 bit.
Sa6S
RCR2.5
Sa6 Bit Select. Set to 1 to report the Sa6 bit at the RLINK pin;
set to 0 to not report the Sa6 bit.
Sa5S
RCR2.4
Sa5 Bit Select. Set to 1 to report the Sa5 bit at the RLINK pin;
set to 0 to not report the Sa5 bit.
Sa4S
RCR2.3
Sa4 Bit Select. Set to 1 to report the Sa4 bit at the RLINK pin;
set to 0 to not report the Sa4 bit.
RBCS
RCR2.2
Receive Side Backplane Clock Select.
0=if RSYSCLK is 1.544 MHz
1=if RSYSCLK is 2.048 MHz
RESE
RCR2.1
Receive Side Elastic Store Enable.
0=elastic store is bypassed
1=elastic store is enabled
-
RCR2.0
Not Assigned. Should be set to 0 when written.
相關(guān)PDF資料
PDF描述
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DS21Q44 制造商:DALLAS 制造商全稱:Dallas Semiconductor 功能描述:Enhanced QUAD E1 FRAMER
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