參數(shù)資料
型號(hào): DS21Q43-ATN
廠商: Maxim Integrated Products
文件頁(yè)數(shù): 3/60頁(yè)
文件大小: 0K
描述: IC FRAMER E1 QUAD 5V 128-TQFP
產(chǎn)品培訓(xùn)模塊: Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
標(biāo)準(zhǔn)包裝: 72
控制器類型: E1 調(diào)幀器
接口: 并行/串行
電源電壓: 4.5 V ~ 5.5 V
電流 - 電源: 32mA
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 128-LQFP
供應(yīng)商設(shè)備封裝: 128-LQFP(14x20)
包裝: 管件
DS21Q43A
11 of 60
Data Bus [D0 to D7] or Address/Data Bus [AD0 to AD7]. In non-multiplexed bus operation (MUX=0),
serves as the data bus. In multiplexed bus operation (MUX=1), serves as an 8-bit multiplexed
address/data bus.
Address Bus [A0 to A5]. In non-multiplexed bus operation (MUX=0), serves as the address bus. In
multiplexed bus operation (MUX=1), these pins are not used and should be tied low.
Bus Type Select [BTS]. Strap high to select Motorola bus timing; strap low to select Intel bus timing.
This pin controls the function of the RD (DS), ALE(AS), and WR (R/ W ) pins. If BTS=1, then these pins
assume the function listed in parentheses ().
Read Input [ RD ] (Data Strobe [DS]).
Framer Selects [FS0 and FS1]. Selects which of the four framers to be accessed.
Chip Selects [ CS ]. Must be low to read or write to any of the four framers.
A6 or Address Latch Enable [ALE] (Address Strobe [AS]). In non-multiplexed bus operation
(MUX=0), serves as the upper address bit. In multiplexed bus operation (MUX=1), serves to demultiplex
the bus on a positive-going edge.
Write Input [ WR ] (Read/Write [R/ W ]).
Positive Supply [VDD]. 5.0 volts ± 0.5 volts.
Signal Ground [VSS]. 0.0 volts.
DS21Q43A FRAMER DECODE Table 1-5
FS1
FS0
FRAMER ACCESSED
0
#0
0
1
#1
1
0
#2
1
#3
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