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參數(shù)資料
| 型號(hào)： | DS2181A |
| 廠商： | Maxim Integrated Products |
| 文件頁數(shù)： | 23/32頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC TXRX CEPT PRIMARY RATE 40-DIP |
| 產(chǎn)品培訓(xùn)模塊： | Lead (SnPb) Finish for COTS Obsolescence Mitigation Program |
| 標(biāo)準(zhǔn)包裝： | 10 |
| 類型： | 收發(fā)器 |
| 驅(qū)動(dòng)器/接收器數(shù)： | 1/1 |
| 規(guī)程： | CEPT |
| 電源電壓： | 4.5 V ~ 5.5 V |
| 安裝類型： | 通孔 |
| 封裝/外殼： | 40-DIP（0.600"，15.24mm） |
| 供應(yīng)商設(shè)備封裝： | 40-PDIP |
| 包裝： | 管件 |
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DS2181A
3 of 32
TRANSMIT PIN DESCRIPTION (40-PIN DIP ONLY) Table 1
PIN
SYMBOL
TYPE
DESCRIPTION
1
TMSYNC
I
Transmit Multiframe Sync. Low-high transition establishes start of
CAS and/or CRC4 multiframe. Can be tied low, allowing internal
multiframe counter to run free.
2
TFSYNC
I
Transmit Frame Sync. Low-high transition every frame period
establishes frame boundaries. Can be tied low, allowing TMSYNC to
establish frame boundaries.
3TCLK
I
Transmit Clock. 2.048 MHz primary clock.
4TCHCLK
O
Transmit Channel Clock. 256 kHz clock which identifies timeslot
boundaries. Useful for parallel-to-serial conversion of channel data.
5TSER
I
Transmit Serial Data. NRZ data input, sampled on falling edges of
TCLK.
6TMO
O
Transmit Multiframe Out. Output of multiframe counter; high
during frame 0, low otherwise.
7TXD
I
Transmit Extra Data. Sampled on falling edge of TCLK during bit
times 5, 7, and 8 of timeslot 16 in frame 0 when CAS signaling is
enabled.
8TSTS
O
Transmit Signaling Timeslot. High during timeslot 16 of every
frame, low otherwise.
9TSD
I
Transmit Signaling Data. CAS signaling data input; sampled on
falling edges of TCLK for insertion into outgoing timeslot 16 when
enabled.
10
TIND
I
Transmit International and National Data. Sampled on falling
edge of TCLK during bit 1 time of timeslot 0 every frame
(international) and/or during bit times 4 through 8 of timeslot 0 during
non-align frames (national) when enabled.
11
TAF
O
Transmit Alignment Frame. High during frames containing the
frame alignment signal, low otherwise.
12
13
TPOS
TNEG
O
Transmit Bipolar Data Outputs. Updated on rising edge of TCLK.
SYCHRONIZER STATUS PIN (44-PIN PLCC ONLY) Table 2A
PIN
SYMBOL
TYPE
DESCRIPTION
3RMSA
O
Receive Multiframe Search Active. This pin will transition high
when the synchronizer searching for the CAS multiframe alignment
word is active.
6RFSA
O
Receive Frame Search Active. This pin will transition high when the
synchronizer searching for the FAS is active.
25
RCTO
O
Receive CRC4 Time Out. This pin will transition high when the
RCTO counter reaches its maximum count of 32. The pin will return
low
when
either the
DS2181AQ
reaches
CRC4
multiframe
synchronization, or if CRC4 is disabled via CRC.2, or if the device is
issued a hardware reset via the RST pin.
28
RCSA
O
Receive CRC4 Search Active. This pin will transition high when the
synchronizer searching for the CRC4 multiframe alignment word is
active.
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| DS2181A+ | 功能描述:網(wǎng)絡(luò)控制器與處理器 IC CEPT Primary Rate Transceiver RoHS:否 制造商:Micrel 產(chǎn)品:Controller Area Network (CAN) 收發(fā)器數(shù)量: 數(shù)據(jù)速率: 電源電流（最大值）:595 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:PBGA-400 封裝:Tray |
| DS2181AN | 功能描述:網(wǎng)絡(luò)控制器與處理器 IC CEPT Primary Rate Transceiver RoHS:否 制造商:Micrel 產(chǎn)品:Controller Area Network (CAN) 收發(fā)器數(shù)量: 數(shù)據(jù)速率: 電源電流（最大值）:595 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:PBGA-400 封裝:Tray |
| DS2181AQ | 功能描述:網(wǎng)絡(luò)控制器與處理器 IC RoHS:否 制造商:Micrel 產(chǎn)品:Controller Area Network (CAN) 收發(fā)器數(shù)量: 數(shù)據(jù)速率: 電源電流（最大值）:595 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:PBGA-400 封裝:Tray |
| DS2181AQ/T&R | 制造商:Maxim Integrated Products 功能描述:CEPT TRANCEIVER-PLCC-TRL - Tape and Reel 制造商:Maxim Integrated Products 功能描述:IC TXRX CEPT PRIMARY RATE 44PLCC |
| DS2181AQ/T&R+ | 制造商:Maxim Integrated Products 功能描述:CEPT TRNSCVR 1TX 1RX 44PLCC - Tape and Reel |
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