參數(shù)資料
型號: DS2180AQ
廠商: MAXIM INTEGRATED PRODUCTS INC
元件分類: Digital Transmission Controller
英文描述: DATACOM, FRAMER, PQCC44
封裝: PLASTIC, LCC-44
文件頁數(shù): 32/35頁
文件大小: 481K
代理商: DS2180AQ
DS2180A
6 of 35
All data transfers are terminated if the CS input transitions high. Port control logic is disabled and SDO is
tri-stated when CS is high.
DATA I/O
Following the eight SCLK cycles that input an address/ command byte to write, a data byte is strobed into
the addressed register on the rising edges of the next eight SCLK cycles. Following an address/command
word to read, contents of the selected register are output on the falling edges of the next eight SCLK
cycles. The SDO pin is tri-stated during device write and may be tied to SDI in applications where the
host processor has a bi-directional I/O pin.
BURST MODE
The burst mode allows all onboard registers to be consecutively read and written by the host processor. A
burst read is used to poll all registers; RSR contents will be unaffected. This feature minimizes device
initialization time on power-up or system reset. Burst mode is initiated when ACB.7 is set and the address
nibble is 0000. Burst is terminated by a low-high transition on CS .
ACB: ADDRESS COMMAND BYTE Figure 2
(MSB)
(LSB)
BM
-
ADD3
ADD2
ADD1
AD0
R/ W
SYMBOL
POSITION
NAME AND DESCRIPTION
BM
ACB.7
Burst Mode. If set (and ACB.1 through ACB.4=0) burst read or
write is enabled.
-
ACB.6
Reserved, must be 0 for proper operation.
-
ACB.5
Reserved, must be 0 for proper operation.
ADD3
ACB.4
MSB of register address.
ADD0
ACB.1
LSB of register address.
R/ W
ACB.0
Read/Write Select.
0 = write addressed register.
1 = read addressed register.
SERIAL PORT READ/WRITE Figure 3
NOTES:
1. SDI sampled on rising edge of SCLK.
2. SDO updated on falling edge of SCLK.
相關(guān)PDF資料
PDF描述
DS2180AQN DATACOM, FRAMER, PQCC44
DS2180A DATACOM, FRAMER, PDIP40
DS2180AN DATACOM, FRAMER, PDIP40
DS2181AN DATACOM, FRAMER, PDIP40
DS2181AQN DATACOM, FRAMER, PQCC44
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