參數(shù)資料
型號: DS2149Q+
廠商: Maxim Integrated Products
文件頁數(shù): 4/32頁
文件大?。?/td> 0K
描述: IC LIU T1/J1 5V 28-PLCC
產(chǎn)品培訓模塊: Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
標準包裝: 37
類型: 線路接口裝置(LIU)
規(guī)程: T1/J1
電源電壓: 4.75 V ~ 5.25 V
安裝類型: 表面貼裝
封裝/外殼: 28-LCC(J 形引線)
供應商設(shè)備封裝: 28-PLCC(11.51x11.51)
包裝: 管件
產(chǎn)品目錄頁面: 1429 (CN2011-ZH PDF)
DS2149
12 of 32
IMR (B010011): Interrupt Mask Register
MSb
LSb
Z16D
JALT
DFMO
B8ZSD
QRSS
AIS
NLOOP
RCL
SYMBOL
POSITION
FUNCTION
Z16D
IMR.7
0 = Enable 16-zero detect interrupt
1 = Disable 16-zero detect interrupt
JALT
IMR.6
0 = Enable jitter-attenuator limit-trip interrupt
1 = Disable jitter-attenuator limit-trip interrupt
DFMO
IMR.5
0 = Enable driver-open interrupt
1 = Disable driver-open interrupt
B8ZSD
IMR.4
0 = Enable B8ZS-detect interrupt
1 = Disable B8ZS-detect interrupt
QRSS
IMR.3
0 = Enable QRSS interrupt
1 = Disable QRSS interrupt
AIS
IMR.2
0 = Enable AIS interrupt
1 = Disable AIS interrupt
NLOOP
IMR.1
0 = Enable network-loopback interrupt
1 = Disable network-loopback interrupt
RCL
IMR.0
0 = Enable receive carrier-loss interrupt
1 = Disable receive carrier-loss interrupt
TSR (B010100): Transition Status Register
MSb
LSb
Z16D
JALT
DFMO
B8ZSD
QRSS
AIS
NLOOP
RCL
SYMBOL
POSITION
FUNCTION
Z16D
TSR.7
Set when the receiver detects 16 consecutive 0s; cleared when
IMR.7 is cleared.
JALT
TSR.6
Set when the jitter attenuator FIFO reaches to within 4 bits of its
limit; cleared when IMR.6 is cleared.
DFMO
TSR.5
Set when SR.5 changes state; cleared when IMR.5 is cleared.
B8ZSD
TSR.4
Set when the receiver detects B8ZS codewords; cleared when
IMR.4 is cleared.
QRSS
TSR.3
Set when SR.3 changes state; cleared when IMR.3 is cleared.
AIS
TSR.2
Set when SR.2 changes state; cleared when IMR.2 is cleared.
NLOOP
TSR.1
Set when SR.1 changes state; cleared when IMR.1 is cleared.
RCL
TSR.0
Set when SR.0 changes state; cleared when IMR.0 is cleared.
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
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