參數(shù)資料
型號(hào): DS21448
廠商: Maxim Integrated Products
文件頁數(shù): 21/60頁
文件大小: 0K
描述: IC LIU QUAD E1/T1/J1 144-BGA
產(chǎn)品培訓(xùn)模塊: Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
標(biāo)準(zhǔn)包裝: 1
類型: 線路接口裝置(LIU)
驅(qū)動(dòng)器/接收器數(shù): 4/4
規(guī)程: T1/E1/J1
電源電壓: 3.135 V ~ 3.465 V
安裝類型: 表面貼裝
封裝/外殼: 144-BGA
供應(yīng)商設(shè)備封裝: 144-TEPBGA(17x17)
包裝: 管件
DS21448 3.3V T1/E1/J1 Quad Line Interface
28 of 60
6. DIAGNOSTICS
6.1 In-Band Loop-Code Generation and Detection
The DS21448 can generate and detect a repeating bit pattern from 1 to 8 or 16 bits in length. To transmit a pattern,
the user loads the pattern into the transmit code definition (TCD1 and TCD2) registers and selects the proper
length of the pattern by setting the TC0 and TC1 bits in the in-band code control (IBCC) register. When generating
a 1-, 2-, 4-, 8-, or 16-bit pattern, the transmit code registers (TCD1 and TCD2) must be filled with the proper code.
Generation of a 1-, 3-, 5-, or 7-bit pattern only requires TCD1 to be filled. Once this is accomplished, the pattern is
transmitted, as long as the TLCE control bit (CCR3.3) is enabled. For example, if the user wished to transmit the
standard loop-up code for CSUs, which is a repeating pattern of ...10000100001..., then 80h would be loaded into
TCD1, and the length would set using TC1 and TC0 in the IBCC register to 5 bits.
The DS21448 can detect two separate repeating patterns to allow for a loop-up code and a loop-down code to be
detected. The user programs the codes in the receive-up code definition (RUPCD1 and RUPCD2) registers and the
receive-down code definition (RDNCD1 and RDNCD2) registers; the length of each pattern is selected through the
IBCC register. The DS21448 detects repeating pattern codes with bit-error rates as high as 1 x 10
-2. The code
detector has a nominal integration period of 48ms, so after approximately 48ms of receiving either code, the proper
status bit (LUP at SR.7 and LDN at SR.6) is set to 1. Normally codes are sent for a period of 5 seconds. It is
recommended that the software poll the DS21448 every 100ms to 1000ms until 5 seconds has elapsed to ensure
the code is continuously present.
IBCC (0AH): In-Band Code Control Register
(MSB)
(LSB)
TC1
TC0
RUP2
RUP1
RUP0
RDN2
RDN1
RDN0
NAME
POSITION
FUNCTION
TC1
IBCC.7
Transmit Code Length Definition Bit 1 (Table 6-A)
TC0
IBCC.6
Transmit Code Length Definition Bit 0. (Table 6-A)
RUP2
IBCC.5
Receive Up Code Length Definition Bit 2 (Table 6-B)
RUP1
IBCC.4
Receive-Up Code Length Definition Bit 1 (Table 6-B)
RUP0
IBCC.3
Receive-Up Code Length Definition Bit 0 (Table 6-B)
RDN2
IBCC.2
Receive-Down Code Length Definition Bit 2 (Table 6-B)
RDN1
IBCC.1
Receive-Down Code Length Definition Bit 1 (Table 6-B)
RDN0
IBCC.0
Receive-Down Code Length Definition Bit 0 (Table 6-B)
D0
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