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參數(shù)資料
| 型號： | DS21349Q+ |
| 廠商： | Maxim Integrated Products |
| 文件頁數(shù)： | 10/35頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC LIU T1/J1 3.3V 28-PLCC |
| 產(chǎn)品培訓(xùn)模塊： | Lead (SnPb) Finish for COTS Obsolescence Mitigation Program |
| 標(biāo)準(zhǔn)包裝： | 37 |
| 類型： | 線路接口裝置（LIU） |
| 電源電壓： | 3.135 V ~ 3.465 V |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 28-LCC（J 形引線） |
| 供應(yīng)商設(shè)備封裝： | 28-PLCC（11.51x11.51） |
| 包裝： | 管件 |
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DS21349
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7. JITTER ATTENUATION
The jitter attenuator only requires a jitter-free clock at 1.544MHz applied to the MCLK input. In
hardware mode, the jitter attenuator is a 32-bit FIFO buffer. Pulling the JASEL pin high places the jitter
attenuator in the receive path. Pulling the JASEL pin low places the jitter attenuator in the transmit path,
floating the JASEL pin disables the jitter attenuator. In software mode, clearing CR1.6 (JASEL0) disables
the jitter attenuator, setting CR1.6 enables the jitter attenuator. If enabled, clearing CR1.7 (JASEL1)
places the jitter attenuator in the transmit path, setting CR1.7 places the jitter attenuator in the receive
path. The jitter attenuator FIFO is 32 bits in length if CR3.2 (JA128) is cleared, 128 bits if set. The device
clocks data in the jitter attenuator using TCLK if placed in the transmit path, and RCLK if placed in the
receive path. Data is clocked out of the jitter attenuator using the dejittered clock produced by the internal
PLL. When the jitter attenuator is within two bits of overflowing or underflowing, the jitter attenuator
will adjust the output clock by one-eighth of a clock cycle. The jitter attenuator adds an average delay of
16 bits if the buffer depth is 32 bits in length, 64 bits if the buffer depth is 128 bits in length. In the event
of an RCL condition, if the jitter attenuator is in the receive path then RCLK is derived from MCLK.
Transition Status register bit TSR.6 (JALT) indicates that the jitter attenuator has adjusted the output
clock. This bit is latched, when set it remains set until the software reads the bit. The JALT can also
produce a hardware interrupt.
8. HARDWARE MODE
The DS21349 operates in hardware mode when the MODE1 pin is pulled low or floated. In hardware
mode, configuration of the device is under control of various input pins. RPOS, RNEG, and RDATA are
valid on the rising edge of RCLK only. Some functions such as INT, clock edge select, and some
diagnostic modes are not available.
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| DS21349Q/T&R+ | 制造商:Maxim Integrated Products 功能描述:FRAMER J1/T1 3.3V 28PLCC - Tape and Reel |
| DS21349Q/T&R | 功能描述:網(wǎng)絡(luò)控制器與處理器 IC RoHS:否 制造商:Micrel 產(chǎn)品:Controller Area Network (CAN) 收發(fā)器數(shù)量: 數(shù)據(jù)速率: 電源電流（最大值）:595 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:PBGA-400 封裝:Tray |
| DS21349Q+ | 功能描述:網(wǎng)絡(luò)控制器與處理器 IC 3.3V E1/T1/J1 Line Interface RoHS:否 制造商:Micrel 產(chǎn)品:Controller Area Network (CAN) 收發(fā)器數(shù)量: 數(shù)據(jù)速率: 電源電流（最大值）:595 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:PBGA-400 封裝:Tray |
| DS21349Q+T&R | 制造商:Maxim Integrated Products 功能描述:FRAMER J1/T1 3.3V 28PLCC - Tape and Reel 制造商:Maxim Integrated Products 功能描述:IC LIU T1/J1 3.3V 28-PLCC |
| DS21349Q+T&R | 功能描述:網(wǎng)絡(luò)控制器與處理器 IC 3.3V E1/T1/J1 Line Interface RoHS:否 制造商:Micrel 產(chǎn)品:Controller Area Network (CAN) 收發(fā)器數(shù)量: 數(shù)據(jù)速率: 電源電流（最大值）:595 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:PBGA-400 封裝:Tray |
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