
DS1884
SFP and PON ONU Controller
with Digital LDD Interface
20
Maxim Integrated
Additionally, TXB, TXP, RSSIC, and RSSIF can right-shift
tion. This allows customers with specified ADC ranges to
calibrate the ADC input gain by a factor of 2n to measure
small signals (thereby reducing the full scale by a factor
of 2n). The DS1884 can then right-shift the results by n
bits (effectively multiplying by a factor of 1/2n) to maintain
Alarms and Warnings
The ADC results (after right-shifting, if used) are com-
pared to the alarm and warning thresholds after each
conversion, and the corresponding alarms and/or warn-
ings are set, which can be programmed to create the
internal signal TXFINT. The status of TXFINT can be read
the signals used to trigger TXFOUT. TXFOUT can be
programmed to cause TXDOUT outputs. These ADC
thresholds are user-programmable, as are the masking
registers that can be used to prevent the alarms from
triggering the TXFOUT and TXDOUT outputs.
ADC Timing
Five analog channels are digitized in a round-robin
fashion in the order as shown in
Figure 2. RSSI is mea-
sured twice to obtain coarse and fine measurements
(RSSIC and RSSIF, respectively). The total time required
TXMON conversion, a 3-wire communication is initi-
ated to toggle the MON_SEL bit (bit 6 in the MAX3710’s
alternate sending laser bias (TXB) and laser power
(TXP) signals to the DS1884’s TXMON input.
Right-Shifting ADC Result
If the weighting of the ADC digital reading must conform to
a predetermined full-scale (PFS) value defined by a stan-
dard’s specification (e.g., SFF-8472), then right-shifting can
be used to adjust the PFS analog measurement range while
maintaining the weighting of the ADC results. The DS1884’s
range is wide enough to cover all requirements; when the
maximum input value is ≤ 1/2 of the full-scale value, right-
shifting can be used to obtain greater accuracy.
For instance, the maximum voltage might be 1/8 the
specified PFS value, so only 1/8 the converter’s range is
effective over this range. An alternative is to calibrate the
ADC’s full-scale range to 1/8 the readable PFS value (by
calibrating an input gain of about 8 using the scale regis-
ters) and use a right-shift value of 3. With this implemen-
tation, the resolution of the measurement is increased by
a factor of 8, and because the result is digitally divided
by 8 by right-shifting, the bit weight of the measurement
still meets the standard’s specification (i.e., SFF-8472).
The right-shift operation on the ADC result is carried
out based on the contents of right-shift control regis-
have 3 bits allocated to set the number of right-shifts.
Up to seven right-shift operations are allowed and are
executed as a part of every conversion before the results
are compared to the high and low alarm levels, or loaded
into their corresponding measurement registers (Lower
Memory, Registers 64h–69h). This is true during the
setup of internal calibration as well as during subsequent
data conversions.
Figure 2. ADC Round-Robin Timing
TEMP
VCC
TXB
RSSIC
TOGGLE MON_SEL
RSSIF
TXP
TEMP
tRR
NOTE: IF VCC LO ALARM OR WARNING IS ENABLED AT POWER-UP, THE ADC ROUND-ROBIN TIMING CYCLES BETWEEN TEMPERATURE AND VCC ONLY UNTIL VCC IS ABOVE
THE VCC LO ALARM THRESHOLD.
TOGGLE MON_SEL