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參數(shù)資料
| 型號： | DS1832N |
| 廠商： | MAXIM INTEGRATED PRODUCTS INC |
| 元件分類： | 電源管理 |
| 英文描述： | 1-CHANNEL POWER SUPPLY SUPPORT CKT, PDIP8 |
| 封裝： | 0.300 INCH, DIP-8 |
| 文件頁數(shù)： | 2/7頁 |
| 文件大?。?/td> | 59K |
| 代理商： | DS1832N |
DS1832
062698 2/7
OPERATION – POWER MONITOR
The DS1832 detects out–of–tolerance power supply
conditions and warns a processor–based system of im-
pending power failure. When VCC falls below a preset
level as defined by TOL, the VCC comparator outputs the
signals RST and RST. When TOL is connected to
ground, the RST and RST signals become active as VCC
falls below 2.98 volts. When TOL is connected to VCC,
the RST and RST signals become active as VCC falls be-
low 2.64 volts. The RST and RST are excellent control
signals for a microprocessor, as processing is stopped at
the last possible moments of valid VCC. On power–up,
RST and RST are kept active for a minimum of 250 ms to
allow the power supply and processor to stabilize.
OPERATION – PUSHBUTTON RESET
The DS1832 provides an input pin for direct connection
to a pushbutton reset (see Figure 2). The pushbutton re-
set input requires an active low signal. Internally, this in-
put is debounced and timed such that RST and RST sig-
nals of at least 250 ms minimum are generated. The
250 ms delay commences as the pushbutton reset input
is released from the low level.
OPERATION – WATCHDOG TIMER
The watchdog timer function forces RST and RST sig-
nals active when the ST input is not clocked within the
predetermined time period. The timeout period is deter-
mined by the condition of the TD pin. if TD is connected
to ground the minimum watchdog timeout would be
62.5 ms, TD floating would yield a minimum timeout of
250 ms, and TD connected to VCC would provide a time-
out of 500 ms minimum. Timeout of the watchdog starts
when RST and RST become inactive. If a high–to–low
transition occurs on the ST input pin prior to time–out,
the watchdog timer is reset and begins to time–out
again. If the watchdog timer is allowed to time–out, then
the RST and RST signals are driven active for a mini-
mum of 250 ms. The ST input can be derived from many
microprocessor outputs. The most typical signals used
are the microprocessor address signals, data signals or
control signals. When the microprocessor functions
normally, these signals would, as a matter of routine,
cause the watchdog to be reset prior to time–out. To
guarantee that the watchdog timer does not time–out, a
high–to–low transition must occur at or less than the
minimum times shown in Table 1. A typical circuit exam-
ple is shown in Figure 4.
The DS1832 watchdog function cannot be disabled.
The watchdog strobe input must be strobed to avoid a
watchdog timeout and reset.
MICROMONITOR BLOCK DIAGRAM Figure 1
TOL
T.C. REFERENCE
LEVEL SENSE
VOLTAGE
DIGITAL
TD
TIME-OUT
ST
PBRST
VCC
TOLERANCE
BIAS
AND
DEBOUNCE
SENSE
COMPARATOR
DELAY
+
–
VCC
RST
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| DS1832S+T&R | 制造商:Maxim Integrated Products 功能描述:PROCESSOR SUPERVISOR 2.88V 35UA 8SOIC - Tape and Reel 制造商:Maxim Integrated Products 功能描述:3.3 VOLT MICRO MONTIOR CHIP 制造商:Maxim Integrated Products 功能描述:IC MICROMONITOR 3.3V 8-SOIC 制造商:Maxim Integrated Products 功能描述:Supervisory Circuits 3.3V MicroMonitor |
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