參數(shù)資料
型號: DS1819BR-10T&R
廠商: MAXIM INTEGRATED PRODUCTS INC
元件分類: 電源管理
英文描述: 1-CHANNEL POWER SUPPLY MANAGEMENT CKT, PDSO5
封裝: SOT-23, 5 PIN
文件頁數(shù): 5/12頁
文件大?。?/td> 237K
代理商: DS1819BR-10T&R
DS1814/DS1819
2 of 8
The DS1814/DS1819 ‘A’ and ‘C’ perform pushbutton reset control. They debounce the pushbutton input
and generate an active reset pulse width of 140ms minimum. The DS1814/9 ‘A’ and ‘B’ versions perform
a watchdog function. The watchdog is an internal timer that forces the reset signals to the active state if
the strobe input does not change state every 1.12 seconds. The watchdog timer function can be disabled
by leaving the watchdog strobe input disconnected.
OPERATION
Power Monitor
The DS1814 detects out-of-tolerance power supply conditions and warns a processor-based system of
impending power failure. When VCC falls below a preset level, a comparator outputs the signal RST (or
RST). RST (or RST) are excellent control signals for a microprocessor, as processing is stopped at the
last possible moment of valid VCC. On power-up, RST (or RST) are kept active for a minimum of 140ms
to allow the power supply and processor to stabilize.
Pushbutton Reset
The DS1814 ‘A’ and ‘C’ provide an input pin for direct connection to a pushbutton reset (see Figure 2).
The pushbutton reset input requires an active low signal. Internally, this input is debounced and timed
such that a RST (or RST) signal of at least 140ms minimum will be generated. The 140ms delay
commences as the pushbutton reset input is released from the low level (see Figure 3).
Watchdog Timer
The DS1814/DS1819 ‘A’ and ‘B’ versions watchdog timer function forces RST (and RST) signal(s)
active when the ST input is not clocked within the 1.12 second watchdog time-out period. Time-out of
the watchdog starts when RST (and RST) become(s) inactive. If a transition occurs on the ST input pin
prior to time-out, the watchdog timer is reset and begins to time out again. If the watchdog timer is
allowed to time out, then the reset output(s) will go active for 140ms. The watchdog can be disabled by
floating (or tri-stating) the ST input.
The ST input can be derived from many microprocessor outputs. The most typical signals used are the
microprocessor data I/O signals and control signals. When the microprocessor functions normally, these
signals would as a matter of routine cause the watchdog to be reset prior to time-out. To guarantee that
the watchdog timer does not time out, a transition must occur at or less than 1.12 seconds. A typical
circuit example is shown in Figure 4. The DS1814/19 watchdog function can be disabled at any time by
tri-starting the strobe input. A sample circuit to disable the watchdog is shown in Figure 6.
相關(guān)PDF資料
PDF描述
DS1855B-010 Dual Nonvolatile Digital Potentiometer and Secure Memory
DS1855B-020 Dual Nonvolatile Digital Potentiometer and Secure Memory
DS1855B-050 Dual Nonvolatile Digital Potentiometer and Secure Memory
DS1855B-100 Dual Nonvolatile Digital Potentiometer and Secure Memory
DS1855E-010 Dual Nonvolatile Digital Potentiometer and Secure Memory
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