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參數(shù)資料
| 型號(hào)： | DS1807S/T&R |
| 廠商： | Maxim Integrated Products |
| 文件頁(yè)數(shù)： | 4/13頁(yè) |
| 文件大?。?/td> | 0K |
| 描述： | IC POT ADDRESS 2X AUDIO 16-SOIC |
| 產(chǎn)品培訓(xùn)模塊： | Lead (SnPb) Finish for COTS Obsolescence Mitigation Program |
| 標(biāo)準(zhǔn)包裝： | 1,000 |
| 接片： | 64 |
| 電阻（歐姆）： | 45k |
| 電路數(shù)： | 2 |
| 溫度系數(shù)： | 標(biāo)準(zhǔn)值 750 ppm/°C |
| 存儲(chǔ)器類型： | 易失 |
| 接口： | I²C（芯片選擇） |
| 電源電壓： | 2.7 V ~ 5.5 V |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 16-SOIC（0.295"，7.50mm 寬） |
| 供應(yīng)商設(shè)備封裝： | 16-SOIC W |
| 包裝： | 帶卷 (TR) |
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DS1807
12 of 13
110499
NOTES:
1. All voltages are referenced to ground.
2. I/O pins of fast mode devices must not obstruct the SDA and SCL lines if VDD is switched off.
3. ICC specified with zero-crossing detection active and operating device serial port in fast mode.
4. ISTBY specified with for VCC equal 3.0V and 5.0V and SDA and SCL are driven to the appropriate
logic levels. ISTBY is specified as the current consumption of the device when SDA and SCL are in the
inactive (high) states.
5. After this period, the first clock pulse is generated.
6. A device must internally provide a hold time of at least 300 ns for the SDA signal (referred to the
VIHMIN of the SCL signal) in order to bridge the undefined region of the falling edge of SCL.
7. The maximum tHD:DAT has only to be met if the device does not stretch the LOW period (tLOW) of the
SCL signal.
8. A fast mode device can be used in a standard mode system, but the requirement tSU:DAT > 250 ns must
then be met. This will automatically be the case if the device does not stretch the LOW period of the
SCL signal. If such a device does stretch the LOW period of the SCL signal, it must output the next
data bit to the SDA line tRMAX + tSU:DAT = 1000+250=1250 ns before the SCL line is released.
9. CB - total capacitance of one bus line in picofarads, timing referenced to (0.9(VCC) and (0.1)(VCC)).
10. Absolute tolerance is used to determine measured wiper voltage versus expected wiper voltage as
determined by wiper position.
11. Tap-to-tap tolerance is used to determine the change in voltage between successive tap positions. The
DS1807 is specified for a
±0.25 dB tap-to-tap tolerance.
12. Typical values are for tA = 25
°C and nominal supply voltage.
13. Address inputs, A0, A1, and A2, should be tied to either VCC or GND depending on the desired
address selections.
14. These parameters are characterized and not 100% tested.
15. Interchannel matching is used to determine the relative difference in dB between the same position on
each potentiometer. The DS1807 is specified for
±0.5 dB Interchannel matching
16. See Figure 9.
17. Valid at 25
°C only.
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| DS1808Z-050/T&R | 功能描述:數(shù)字電位計(jì) IC RoHS:否 制造商:Maxim Integrated 電阻:200 Ohms 溫度系數(shù):35 PPM / C 容差:25 % POT 數(shù)量:Dual 每 POT 分接頭:256 弧刷存儲(chǔ)器:Volatile 緩沖刷: 數(shù)字接口:Serial (3-Wire, SPI) 描述/功能:Dual Volatile Low Voltage Linear Taper Digital Potentiometer 工作電源電壓:1.7 V to 5.5 V 電源電流:27 uA 最大工作溫度:+ 125 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:TQFN-16 封裝:Reel |
| DS1808Z-050+ | 功能描述:數(shù)字電位計(jì) IC Dual Log RoHS:否 制造商:Maxim Integrated 電阻:200 Ohms 溫度系數(shù):35 PPM / C 容差:25 % POT 數(shù)量:Dual 每 POT 分接頭:256 弧刷存儲(chǔ)器:Volatile 緩沖刷: 數(shù)字接口:Serial (3-Wire, SPI) 描述/功能:Dual Volatile Low Voltage Linear Taper Digital Potentiometer 工作電源電壓:1.7 V to 5.5 V 電源電流:27 uA 最大工作溫度:+ 125 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:TQFN-16 封裝:Reel |
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