- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄97863 > DS17285S-5 (DALLAS SEMICONDUCTOR) 1 TIMER(S), REAL TIME CLOCK, PDSO24 PDF資料下載
參數(shù)資料
| 型號(hào)： | DS17285S-5 |
| 廠商： | DALLAS SEMICONDUCTOR |
| 元件分類： | Timer or RTC |
| 英文描述： | 1 TIMER(S), REAL TIME CLOCK, PDSO24 |
| 封裝： | SOIC-24 |
| 文件頁(yè)數(shù)： | 11/38頁(yè) |
| 文件大小： | 415K |
| 代理商： | DS17285S-5 |
第1頁(yè)第2頁(yè)第3頁(yè)第4頁(yè)第5頁(yè)第6頁(yè)第7頁(yè)第8頁(yè)第9頁(yè)第10頁(yè)當(dāng)前第11頁(yè)第12頁(yè)第13頁(yè)第14頁(yè)第15頁(yè)第16頁(yè)第17頁(yè)第18頁(yè)第19頁(yè)第20頁(yè)第21頁(yè)第22頁(yè)第23頁(yè)第24頁(yè)第25頁(yè)第26頁(yè)第27頁(yè)第28頁(yè)第29頁(yè)第30頁(yè)第31頁(yè)第32頁(yè)第33頁(yè)第34頁(yè)第35頁(yè)第36頁(yè)第37頁(yè)第38頁(yè)
DS17285/DS17287
19 of 38
RAM CLEAR
The DS17285/DS17287 provides a RAM clear function for the 114 bytes of user RAM. When enabled,
this function can be performed regardless of the condition of the VCC pin.
The RAM clear function is enabled or disabled via the RAM Clear Enable bit (RCE; bank 1, register
04BH). When this bit is set to a logic 1, the 114 bytes of user RAM will be cleared (all bits set to 1)
when an active low transition is sensed on the RCLR pin. This action will have no effect on either the
clock/calendar settings or upon the contents of the extended RAM. The RAM clear Flag (RF, bank 1,
register 04AH) will be set when the RAM clear operation has been completed. If VCC is present at the
time of the RAM clear and RIE=1, the IRQ line will also be driven low upon completion. The interrupt
condition can be cleared by writing a 0 to the RF bit. The IRQ line will then return to its inactive high
level provided there are no other pending interrupts. Once the RCLR pin is activated, all read/write
accesses are locked out for a minimum recover time, specified as tREC in the Electrical Characteristics
section.
When RCE is cleared to zero, the RAM clear function is disabled. The state of the RCLR pin will have
no effect on the contents of the user RAM, and transitions on the RCLR pin have no effect on RF.
2k X 8 EXTENDED RAM
The DS17285/DS17287 provides 2k x 8 of on-chip SRAM which is controlled as nonvolatile storage
sustained from a lithium battery. On power-up, the RAM is taken out of write protect status by the
internal power OK signal (POK) generated from the write-protect circuitry.
The on-chip 2k x 8 nonvolatile SRAM is accessed via the eight multiplexed address/data lines AD7 to
AD0. Access to the SRAM is controlled by three on-chip latch registers. Two registers are used to hold
the SRAM address, and the other register is used to hold read/write data. The SRAM address space is
from 00h to 07FFh.
Access to the extended 2k x 8 RAM is controlled via three of the Dallas registers shown in Figure 4. The
Dallas registers in bank 1 must first be selected by setting the DV0 bit in register A to a logic 1. The
11-bit address of the RAM location to be accessed must be loaded into the extended RAM address
registers located at 50h and 51h. The least significant address byte should be written to location 50h, and
the most significant 3 bits (right-justified) should be loaded in location 51h. Data in the addressed
location may be read by performing a read operation from location 53h, or written to by performing a
write operation to location 53h. Data in any addressed location may be read or written repeatedly without
changing the address in location 50h and 51h.
To read or write consecutive extended RAM locations, a burst mode feature can be enabled to increment
the extended RAM address. To enable the burst mode feature, set the BME bit in the extended control
register 4Ah, to a logic 1. With burst mode enabled, write the extended RAM starting address location to
registers 50h and 51h. Then read or write the extended RAM data from/to register 53h. The extended
RAM address locations are automatically incremented on the rising edge of RD or WR only when
register 53h is being accessed. Refer to the Burst Mode Timing Waveform.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| DS17285SN-5 | 1 TIMER(S), REAL TIME CLOCK, PDSO24 |
| DS17285EN-3 | 1 TIMER(S), REAL TIME CLOCK, PDSO28 |
| DS17285S-3 | 1 TIMER(S), REAL TIME CLOCK, PDSO24 |
| DS1742-100 | 0 TIMER(S), REAL TIME CLOCK, PDIP24 |
| DS1742W-120 | 0 TIMER(S), REAL TIME CLOCK, PDIP24 |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| DS17285S-5/T&R | 制造商:Maxim Integrated Products 功能描述:IC RTC 5V 2K NV RAM 24-SOIC |
| DS17285S-5/T&R | 功能描述:實(shí)時(shí)時(shí)鐘 RoHS:否 制造商:Microchip Technology 功能:Clock, Calendar. Alarm RTC 總線接口:I2C 日期格式:DW:DM:M:Y 時(shí)間格式:HH:MM:SS RTC 存儲(chǔ)容量:64 B 電源電壓-最大:5.5 V 電源電壓-最小:1.8 V 最大工作溫度:+ 85 C 最小工作溫度: 安裝風(fēng)格:Through Hole 封裝 / 箱體:PDIP-8 封裝:Tube |
| DS17285S-5+ | 功能描述:實(shí)時(shí)時(shí)鐘 3V/5V RTC K Multiplexed Kick-S RoHS:否 制造商:Microchip Technology 功能:Clock, Calendar. Alarm RTC 總線接口:I2C 日期格式:DW:DM:M:Y 時(shí)間格式:HH:MM:SS RTC 存儲(chǔ)容量:64 B 電源電壓-最大:5.5 V 電源電壓-最小:1.8 V 最大工作溫度:+ 85 C 最小工作溫度: 安裝風(fēng)格:Through Hole 封裝 / 箱體:PDIP-8 封裝:Tube |
| DS17285S-5+T&R | 制造商:Maxim Integrated Products 功能描述:REAL TIME CLOCK MULTIPLEXED 2KBYTE 24SOIC - Tape and Reel 制造商:Maxim Integrated Products 功能描述:Maxim Integrated DS17285S-5+T&R Real Time Clocks (RTC) 制造商:Maxim Integrated Products 功能描述:IC RTC 5V 2K NV RAM 24-SOIC |
| DS17285S-5+T&R | 功能描述:實(shí)時(shí)時(shí)鐘 3V/5V RTC K Multiplexed Kick-S RoHS:否 制造商:Microchip Technology 功能:Clock, Calendar. Alarm RTC 總線接口:I2C 日期格式:DW:DM:M:Y 時(shí)間格式:HH:MM:SS RTC 存儲(chǔ)容量:64 B 電源電壓-最大:5.5 V 電源電壓-最小:1.8 V 最大工作溫度:+ 85 C 最小工作溫度: 安裝風(fēng)格:Through Hole 封裝 / 箱體:PDIP-8 封裝:Tube |
發(fā)布緊急采購(gòu)，3分鐘左右您將得到回復(fù)。