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參數(shù)資料
| 型號： | DS1558Y+TRL |
| 廠商： | Maxim Integrated Products |
| 文件頁數(shù)： | 2/18頁 |
| 文件大小： | 0K |
| 描述： | IC RTC W/NV RAM 5V 48-TQFP |
| 產(chǎn)品培訓(xùn)模塊： | Lead (SnPb) Finish for COTS Obsolescence Mitigation Program |
| 標(biāo)準(zhǔn)包裝： | 2,000 |
| 類型： | 時鐘/日歷 |
| 特點： | 警報器，閏年，監(jiān)視計時器，Y2K |
| 時間格式： | HH:MM:SS（24 小時） |
| 數(shù)據(jù)格式： | YY-MM-DD-dd |
| 接口： | 并聯(lián) |
| 電源電壓： | 4.5 V ~ 5.5 V |
| 電壓 - 電源，電池： | 2.5 V ~ 3.7 V |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 48-LQFP |
| 供應(yīng)商設(shè)備封裝： | 48-LQFP（7x7） |
| 包裝： | 帶卷 (TR) |
DS1558
10 of 18
Figure 4. BACKUP MODE ALARM WAVEFORMS
he user programs the watchdog
ount of timeout into the 8-bit watchdog register (address 7FFF7h). The
sto
= 1 second, and
ation of the 5-bit
watchdog register
ecified period, the
or the watchdog register (7FFF7h) is read or written.
a 0, the w
og
USING THE WATCHDOG TIMER
The watchdog timer can be used to detect an out-of-control processor. T
timer by setting the desired am
five watchdog register bits BMB4–BMB0
re a binary multiplier and the two lower-order bits
RB1–RB0 select the resolution, where 00 = 1/16 second, 01 = 1/4 second, 10
11 = 4 seconds. The watchdog timeout value is then determined by the multiplic
multiplier value with the 2-bit resolution value. (For example: writing 00001110 in the
= 3 x 1 second or 3 seconds.) If the processor does not reset the timer within the sp
watchdog flag (WF) is set and a processor interrupt is generated and stays active until either WF is read
The MSB of the watchdog register is the watchdog steering bit (WDS). When set to
activates the
atchd
IRQ
/FT output when the watchdog times out. WDS should not be written
be initialized to a 0 if the watchdog function is enabled.
hdog register. The
0h to the watchdog
atchdog register is
POWER-ON DEFAULT STATES
Upon application of power to the device, the following register bits are set to a 0:
WDS = 0, BMB0–BMB4 = 0, RB0–RB1 = 0, AE = 0, and ABE = 0
All other bits are undefined.
to a 1, and should
The watchdog timer resets when the processor performs a read or write of the watc
timeout period then starts over. The watchdog timer is disabled by writing a value of 0
register. The watchdog function is automatically disabled upon power-up and the w
cleared.
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