參數(shù)資料
型號: DS1556P
廠商: MAXIM INTEGRATED PRODUCTS INC
元件分類: Timer or RTC
英文描述: REAL TIME CLOCK, DMA34
封裝: POWERCAP MODULE-34
文件頁數(shù): 17/20頁
文件大?。?/td> 282K
代理商: DS1556P
DS1556
6 of 20
DS1556 REGISTER MAP Table 2
DATA
ADDRESS
B7
B6
B5
B4
B3
B2
B1
B0
FUNCTION/RANGE
1FFFFh
10 Year
YEAR
00-99
1FFFEh
X
10 M
MONTH
01-12
1FFFDh
X
10 Date
DATE
01-31
1FFFCh
X
FT
X
DAY
01-07
1FFFBh
X
10 HOUR
HOUR
00-23
1FFFAh
X
10 MINUTES
MINUTES
00-59
1FFF9h
OSC
10 SECONDS
SECONDS
00-59
1FFF8h
W
R
10 CENTURY
CENTURY
CONTROL
00-39
1FFF7h
WDS
BMB4
BMB3
BMB2
BMB
1
BMB0
RB
1
RB0
WATCHDOG
1FFF6h
AE
Y
ABE
Y
INTERRUPTS
1FFF5h
AM4
Y
10 DATE
DATE
ALARM DATE
01-31
1FFF4h
AM3
Y
10 HOURS
HOURS
ALARM HOURS
00-23
1FFF3h
AM2
10 MINUTES
MINUTES
ALARM MINUTES
00-59
1FFF2h
AM1
10 SECONDS
SECONDS
ALARM SECONDS
00-59
1FFF1h
Y
UNUSED
1FFF0h
WF
AF
0
BLF
0
FLAGS
X = Unused, read/writable under Write and Read
AE = Alarm Flag Enable
bit control
Y = Unused, read/writable without Write and Read
FT = Frequency Test bit
bit control
OSC
= Oscillator start/stop bit
ABE = Alarm in battery Back-up mode enable
W = Write bit
AM1-AM4 = Alarm Mask bits
R = Read bit
WF = Watchdog Flag
WDS = Watchdog Steering bit
AF = Alarm Flag
BMB0-BMB4 = Watchdog Multiplier bits
0 = 0 and are read only
RB0-RB1 = Watchdog Resolution bits
BLF = Battery Low Flag
CLOCK OSCILLATOR CONTROL
The Clock oscillator may be stopped at any time. To increase the shelf life of the backup lithium battery
source, the oscillator can be turned off to minimize current drain from the battery. The OSC bit is the
MSB of the Seconds Register (B7 of 1FFF9h). Setting it to a 1 stops the oscillator, setting to a 0 starts the
oscillator. The DS1556 is shipped from Dallas Semiconductor with the clock oscillator turned off, OSC
bit set to a 1.
READING THE CLOCK
When reading the RTC data, it is recommended to halt updates to the external set of double-buffered RTC
Registers. This puts the external registers into a static state allowing data to be read without register
values changing during the read process. Normal updates to the internal registers continue while in this
state. External updates are halted when a 1 is written into the read bit, B6 of the Control Register
(1FFF8h). As long as a 1 remains in the Control Register read bit, updating is halted. After a halt is
issued, the registers reflect the RTC count (day, date, and time) that was current at the moment the halt
command was issued. Normal updates to the external set of registers will resume within 1 second after the
read bit is set to a 0 for a minimum of 500
s. The read bit must be a zero for a minimum of 500 s to
ensure the external registers will be updated.
相關(guān)PDF資料
PDF描述
DS1557WP-120 0 TIMER(S), REAL TIME CLOCK, DMA34
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