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參數(shù)資料
| 型號： | DS1481S/T&R |
| 廠商： | Maxim Integrated Products |
| 文件頁數(shù)： | 9/10頁 |
| 文件大小： | 0K |
| 描述： | IC BUS MASTER 1 WIRE 14-SOIC |
| 標準包裝： | 2,500 |
| 接口： | 1 線 |
| 電源電壓： | 2.7 V ~ 5.5 V |
| 封裝/外殼： | 14-SOIC（0.154"，3.90mm 寬） |
| 供應商設備封裝： | 14-SOIC |
| 包裝： | 帶卷 (TR) |
| 安裝類型： | 表面貼裝 |
DS1481
8 of 10
DETAILED PIN DESCRIPTION
PIN
TYPE
DESCRIPTION
VCC
DC supply voltage.
ENI
I
Chip enable, driven low to begin 1-Wire I/O.
O1/BSY1
O
Driven low during time slot (to indicate a DS1481 busy
condition). Set to state of I1 after time slot has finished.
O1/BSY1 will go low after D/CLK goes low if sample of I/O
communication was low. Returns to state of I1 when ENI
goes back high (see Figure 1).
O2/BSY2
O
Driven low during time slot (to indicate a DS1481 busy
condition). Set to state of I2 after time slot has finished.
O2/BSY2 will go low after D/CLK goes low if sample of I/O
communication was low. Returns to state of I2 when ENI
goes back high (see Figure 1).
D/CLK
I
Data/Clock pin. Used to specify type of time slot before
communication begins. After the time slot has been
completed this pin is driven low in order to solicit the result
of the time slot.
RES
I
Set low (before ENI is driven low) to specify that a reset
pulse should be generated on the I/O pin.
GND
System ground.
I1
I
Can be connected to the O1/BSY1 of another DS1481. May
also be connected to parallel port printer’s BUSY signal.
Internally pulled high via a weak resistor.
I2
I
Can be connected to the O2/BSY2 of another DS1481. Can
also be connected to a parallel port printer SELECT OUT
signal. Internally pulled high via a weak resistor.
ENO
O
Set to ENI if not the last part on port. Open-drain output with
weak internal pullup resistor.
I/O
1-Wire I/O line. Bidirectional line with open-drain output.
Not
Recommended
for
New
Design
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| DS1482 | 制造商:DALLAS 制造商全稱:Dallas Semiconductor 功能描述:1-Wire Level Shifter and Line Driver with Load Sensor |
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