I2C RTC/Supervisor with Trickle Charger and 512 Bytes EEPROM 6 Maxim Integrated " />
參數(shù)資料
型號: DS1388Z-3+T&R
廠商: Maxim Integrated Products
文件頁數(shù): 16/19頁
文件大小: 0K
描述: IC RTC I2C W/CHARGER 8-SOIC
產(chǎn)品培訓(xùn)模塊: Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
標(biāo)準(zhǔn)包裝: 2,500
類型: 時鐘/日歷
特點: EEPROM,閏年,監(jiān)控器,涓流充電器,監(jiān)視計時器
存儲容量: 512B
時間格式: HH:MM:SS:hh(12/24 小時)
數(shù)據(jù)格式: YY-MM-DD-dd
接口: I²C,2 線串口
電源電壓: 2.7 V ~ 3.3 V
電壓 - 電源,電池: 1.3 V ~ 5.5 V
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 8-SOIC(0.154",3.90mm 寬)
供應(yīng)商設(shè)備封裝: 8-SOIC
包裝: 帶卷 (TR)
I2C RTC/Supervisor with Trickle Charger
and 512 Bytes EEPROM
6
Maxim Integrated
DS1388
WARNING: Under no circumstances are negative undershoots, of any
amplitude, allowed when device is in write protection.
Note 2:
Limits at -40°C are guaranteed by design and are not production tested.
Note 3:
All voltages are referenced to ground.
Note 4:
Measured at VCC = typ, VBACKUP = 0V, register 0Ah, block 0h = A5h.
Note 5:
The use of the 250
Ω trickle-charge resistor is not allowed at VCC > 3.63V and should not be enabled.
Note 6:
Measured at VCC = typ, VBACKUP = 0V, register 0Ah, block 0h = A6h.
Note 7:
Measured at VCC = typ, VBACKUP = 0V, register 0Ah, block 0h = A7h.
Note 8:
The RST pin has an internal 50k
Ω pullup resistor to VCC.
Note 9:
ICCA—SCL clocking at max frequency = 400kHz.
Note 10: Specified with I2C bus inactive.
Note 11: Measured with a 32.768kHz crystal attached to X1 and X2.
Note 12: After this period, the first clock pulse is generated.
Note 13: A device must internally provide a hold time of at least 300ns for the SDA signal (referred to the VIHMIN of the SCL signal)
to bridge the undefined region of the falling edge of SCL.
Note 14: The maximum tHD:DAT need only be met if the device does not stretch the LOW period (tLOW) of the SCL signal.
Note 15: A fast-mode device can be used in a standard-mode system, but the requirement tSU:DAT ≥ 250ns must then be met. This
is automatically the case if the device does not stretch the LOW period of the SCL signal. If such a device does stretch the
LOW period of the SCL signal, it must output the next data bit to the SDA line tR(MAX) + tSU:DAT = 1000 + 250 = 1250ns
before the SCL line is released.
Note 16: CB—total capacitance of one bus line in pF.
Note 17: The parameter tOSF is the period of time that the oscillator must be stopped for the OSF flag to be set over the voltage
range of 0V
≤ VCC ≤ VCC(MAX) and 1.3V ≤ VBACKUP ≤ 3.7V.
Note 18: If the oscillator is disabled or stopped, RST goes inactive after tRST plus the startup time of the oscillator.
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