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參數(shù)資料
| 型號(hào)： | DS1350YP-70 |
| 廠商： | DALLAS SEMICONDUCTOR |
| 元件分類： | Static RAM |
| 英文描述： | 512K X 8 NON-VOLATILE SRAM MODULE, 70 ns, DMA34 |
| 封裝： | POWERCAP MODULE-34 |
| 文件頁(yè)數(shù)： | 11/12頁(yè) |
| 文件大小： | 228K |
| 代理商： | DS1350YP-70 |
DS1350Y/AB
8 of 12
POWER-DOWN/POWER-UP TIMING
(tA: See Note 10)
PARAMETER
SYMBOL
MIN
TYP
MAX
UNITS
NOTES
VCC Fail Detect to CE and WE Inactive
tPD
1.5
s
11
VCC slew from VTP to 0V
tF
150
s
VCC Fail Detect to RST Active
tRPD
15
s
14
VCC slew from 0V to VTP
tR
150
s
VCC Valid to CE and WE Inactive
tPU
2ms
VCC Valid to End of Write Protection
tREC
125
ms
VCC Valid to RST Inactive
tRPU
150
200
350
ms
14
VCC Valid to BW Valid
tBPU
1s
14
BATTERY WARNING TIMING
(tA: See Note 10)
PARAMETER
SYMBOL
MIN
TYP
MAX
UNITS
NOTES
Battery Test Cycle
tBTC
24
hr
Battery Test Pulse Width
tBTPW
1s
Battery Test to BW Active
tBW
1s
(tA=25
°C)
PARAMETER
SYMBOL
MIN
TYP
MAX
UNITS
NOTES
Expected Data Retention Time
tDR
10
years
9
WARNING:
Under no circumstance are negative undershoots, of any amplitude, allowed when device is in battery
backup mode.
NOTES:
1.
WE
is high for a Read Cycle.
2. OE = VIH or VIL. If OE = VIH during write cycle, the output buffers remain in a high-impedance state.
3. tWP is specified as the logical AND of CE and WE . tWP is measured from the latter of CE or WE
going low to the earlier of CE or WE going high.
4. tDS are measured from the earlier of CE or WE going high.
5. These parameters are sampled with a 5 pF load and are not 100% tested.
6. If the CE low transition occurs simultaneously with or latter than the WE low transition, the output
buffers remain in a high-impedance state during this period.
7. If the CE high transition occurs prior to or simultaneously with the WE high transition, the output
buffers remain in high-impedance state during this period.
8. If WE is low or the WE low transition occurs prior to or simultaneously with the CE low transition,
the output buffers remain in a high-impedance state during this period.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| DS1350ABP-70 | 512K X 8 NON-VOLATILE SRAM MODULE, 70 ns, DMA34 |
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| DS1350YP-70+ | 功能描述:NVRAM 4096K NV SRAM w/Battery Monitor RoHS:否 制造商:Maxim Integrated 數(shù)據(jù)總線寬度:8 bit 存儲(chǔ)容量:1024 Kbit 組織:128 K x 8 接口類型:Parallel 訪問(wèn)時(shí)間:70 ns 電源電壓-最大:5.5 V 電源電壓-最小:4.5 V 工作電流:85 mA 最大工作溫度:+ 70 C 最小工作溫度:0 C 封裝 / 箱體:EDIP 封裝:Tube |
| DS1350YP-70IND | 功能描述:NVRAM 4096K NV SRAM w/Battery Monitor RoHS:否 制造商:Maxim Integrated 數(shù)據(jù)總線寬度:8 bit 存儲(chǔ)容量:1024 Kbit 組織:128 K x 8 接口類型:Parallel 訪問(wèn)時(shí)間:70 ns 電源電壓-最大:5.5 V 電源電壓-最小:4.5 V 工作電流:85 mA 最大工作溫度:+ 70 C 最小工作溫度:0 C 封裝 / 箱體:EDIP 封裝:Tube |
| DS1350YP-70-IND | 制造商:DALLAS 制造商全稱:Dallas Semiconductor 功能描述:4096k Nonvolatile SRAM with Battery Monitor |
| DS1350YP-70IND+ | 功能描述:NVRAM 4096K NV SRAM w/Battery Monitor RoHS:否 制造商:Maxim Integrated 數(shù)據(jù)總線寬度:8 bit 存儲(chǔ)容量:1024 Kbit 組織:128 K x 8 接口類型:Parallel 訪問(wèn)時(shí)間:70 ns 電源電壓-最大:5.5 V 電源電壓-最小:4.5 V 工作電流:85 mA 最大工作溫度:+ 70 C 最小工作溫度:0 C 封裝 / 箱體:EDIP 封裝:Tube |
| DS1350YP-C01 | 功能描述:NVRAM RoHS:否 制造商:Maxim Integrated 數(shù)據(jù)總線寬度:8 bit 存儲(chǔ)容量:1024 Kbit 組織:128 K x 8 接口類型:Parallel 訪問(wèn)時(shí)間:70 ns 電源電壓-最大:5.5 V 電源電壓-最小:4.5 V 工作電流:85 mA 最大工作溫度:+ 70 C 最小工作溫度:0 C 封裝 / 箱體:EDIP 封裝:Tube |
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