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參數(shù)資料
| 型號： | DS1350YP-100 |
| 廠商： | MAXIM INTEGRATED PRODUCTS INC |
| 元件分類： | Static RAM |
| 英文描述： | 512K X 8 NON-VOLATILE SRAM MODULE, 100 ns, DMA34 |
| 封裝： | POWERCAP MODULE-34 |
| 文件頁數(shù)： | 7/14頁 |
| 文件大?。?/td> | 287K |
| 代理商： | DS1350YP-100 |
DS1350Y/AB
2 of 12
READ MODE
The DS1350 devices execute a read cycle whenever WE (Write Enable) is inactive (high) and CE (Chip
Enable) and OE (Output Enable) are active (low). The unique address specified by the 19 address inputs
(A0 -A18) defines which of the 524,288 bytes of data is to be accessed. Valid data will be available to the
eight data output drivers within tACC (Access Time) after the last address input signal is stable, providing
that CE and OE (Output Enable) access times are also satisfied. If OE and CE access times are not
satisfied, then data access must be measured from the later-occurring signal ( CE or OE ) and the limiting
parameter is either tCO for CE or tOE for OE rather than address access.
WRITE MODE
The DS1350 devices execute a write cycle whenever the WE and CE signals are in the active (low) state
after address inputs are stable. The later-occurring falling edge of CE or WE will determine the start of
the write cycle. The write cycle is terminated by the earlier rising edge of CE or WE . All address inputs
must be kept valid throughout the write cycle. WE must return to the high state for a minimum recovery
time (tWR) before another cycle can be initiated. The OE control signal should be kept inactive (high)
during write cycles to avoid bus contention. However, if the output drivers are enabled ( CE and OE
active) then WE will disable the outputs in tODW from its falling edge.
DATA RETENTION MODE
The DS1350AB provides full functional capability for VCC greater than 4.75V and write protects by 4.5V.
The DS1350Y provides full functional capability for VCC greater than 4.5V and write protects by 4.25V.
Data is maintained in the absence of VCC without any additional support circuitry. The NV SRAMs
constantly monitor VCC. Should the supply voltage decay, the NV SRAMs automatically write protect
themselves, all inputs become “don’t care,” and all outputs become high-impedance. As VCC falls below
approximately 2.7V, the power switching circuit connects the lithium energy source to RAM to retain
data. During power-up, when VCC rises above approximately 2.7V, the power switching circuit connects
external VCC to the RAM and disconnects the lithium energy source. Normal RAM operation can resume
after VCC exceeds 4.75V for the DS1350AB and 4.5V for the DS1350Y.
SYSTEM POWER MONITORING
DS1350 devices have the ability to monitor the external VCC power supply. When an out-of-tolerance
power supply condition is detected, the NV SRAMs warn a processor-based system of impending power
failure by asserting RST . On power-up, RST is held active for 200ms nominal to prevent system
operation during power-on transients and to allow tREC to elapse. RST has an open drain output driver.
BATTERY MONITORING
The DS1350 devices automatically perform periodic battery voltage monitoring on a 24-hour time
interval. Such monitoring begins within tREC after VCC rises above VTP and is suspended when power
failure occurs.
After each 24-hour period has elapsed, the battery is connected to an internal 1M
W test resistor for one
second. During this one second, if battery voltage falls below the battery voltage trip point (2.6V), the
battery warning output BW is asserted. Once asserted, BW remains active until the module is replaced.
The battery is still retested after each VCC power-up, however, even if BW is active. If the battery voltage
is found to be higher than 2.6V during such testing, BW is de-asserted and regular 24-hour testing
resumes. BW has an open drain output driver.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| DS1350ABP-100 | 512K X 8 NON-VOLATILE SRAM MODULE, 100 ns, DMA34 |
| DS1350YP-70 | 512K X 8 NON-VOLATILE SRAM MODULE, 70 ns, DMA34 |
| DS1350ABP-70 | 512K X 8 NON-VOLATILE SRAM MODULE, 70 ns, DMA34 |
| DS1384FP-12 | 1 TIMER(S), REAL TIME CLOCK, PQFP44 |
| DS1386-32-120 | 0 TIMER(S), REAL TIME CLOCK, PDIP32 |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| DS1350YP-100+ | 功能描述:NVRAM 4096K NV SRAM w/Battery Monitor RoHS:否 制造商:Maxim Integrated 數(shù)據(jù)總線寬度:8 bit 存儲容量:1024 Kbit 組織:128 K x 8 接口類型:Parallel 訪問時間:70 ns 電源電壓-最大:5.5 V 電源電壓-最小:4.5 V 工作電流:85 mA 最大工作溫度:+ 70 C 最小工作溫度:0 C 封裝 / 箱體:EDIP 封裝:Tube |
| DS1350YP-100-IND | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:NVRAM (Battery Based) |
| DS1350YP-70 | 功能描述:NVRAM 4096K NV SRAM w/Battery Monitor RoHS:否 制造商:Maxim Integrated 數(shù)據(jù)總線寬度:8 bit 存儲容量:1024 Kbit 組織:128 K x 8 接口類型:Parallel 訪問時間:70 ns 電源電壓-最大:5.5 V 電源電壓-最小:4.5 V 工作電流:85 mA 最大工作溫度:+ 70 C 最小工作溫度:0 C 封裝 / 箱體:EDIP 封裝:Tube |
| DS1350YP-70+ | 功能描述:NVRAM 4096K NV SRAM w/Battery Monitor RoHS:否 制造商:Maxim Integrated 數(shù)據(jù)總線寬度:8 bit 存儲容量:1024 Kbit 組織:128 K x 8 接口類型:Parallel 訪問時間:70 ns 電源電壓-最大:5.5 V 電源電壓-最小:4.5 V 工作電流:85 mA 最大工作溫度:+ 70 C 最小工作溫度:0 C 封裝 / 箱體:EDIP 封裝:Tube |
| DS1350YP-70IND | 功能描述:NVRAM 4096K NV SRAM w/Battery Monitor RoHS:否 制造商:Maxim Integrated 數(shù)據(jù)總線寬度:8 bit 存儲容量:1024 Kbit 組織:128 K x 8 接口類型:Parallel 訪問時間:70 ns 電源電壓-最大:5.5 V 電源電壓-最小:4.5 V 工作電流:85 mA 最大工作溫度:+ 70 C 最小工作溫度:0 C 封裝 / 箱體:EDIP 封裝:Tube |
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