2C Serial Real-Time Clock 10 of 20 Table 2. Crystal Specifications* PARAMETER SYMBOL MIN TYP M" />
參數(shù)資料
型號(hào)： DS1339C-2#
廠商： Maxim Integrated Products
文件頁(yè)數(shù)： 2/20頁(yè)
文件大?。?/td> 0K
描述： IC RTC I2C W/ALARM 16-SOIC
產(chǎn)品培訓(xùn)模塊： Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
標(biāo)準(zhǔn)包裝： 45
類型： 時(shí)鐘/日歷
特點(diǎn)： 警報(bào)器，閏年，方波輸出，涓流充電器
時(shí)間格式： HH:MM:SS（12/24 小時(shí)）
數(shù)據(jù)格式： YY-MM-DD-dd
接口： I²C，2 線串口
電源電壓： 1.8 V ~ 2.2 V
電壓 - 電源，電池： 1.3 V ~ 3.7 V
工作溫度： -40°C ~ 85°C
安裝類型： 表面貼裝
封裝/外殼： 16-SOIC（0.295"，7.50mm 寬）
供應(yīng)商設(shè)備封裝： 16-SOIC W
包裝： 管件
DS1339 I
2C Serial Real-Time Clock
10 of 20
Table 2. Crystal Specifications*
PARAMETER
SYMBOL
MIN
TYP
MAX
UNITS
Nominal Frequency
fO
32.768
kHz
Series Resistance
ESR
50
k
Load Capacitance
CL
6
pF
*The crystal, traces, and crystal input pins should be isolated from RF generating signals. Refer to
Application Note 58: Crystal Considerations for Dallas Real-Time Clocks for additional specifications.
CLOCK ACCURACY
The accuracy of the clock is dependent upon the accuracy of the crystal and the accuracy of the match between
the capacitive load of the oscillator circuit and the capacitive load for which the crystal was trimmed. Additional
error is added by crystal frequency drift caused by temperature shifts. External circuit noise coupled into the
oscillator circuit may result in the clock running fast. Figure 4 shows a typical PC board layout for isolating the
crystal and oscillator from noise. Refer to Application Note 58: Crystal Considerations with Dallas Real-Time
Clocks for detailed information
DS1339C ONLY
The DS1339C integrates a standard 32,768Hz crystal in the package. Typical accuracy at nominal VCC and +25°C
is approximately 10ppm. Refer to Application Note 58 for information about crystal accuracy vs. temperature.
Figure 4. Typical PC Board Layout for Crystal
LOCAL GROUND PLANE (LAYER 2)
CRYSTAL
X1
X2
GND
NOTE: AVOID ROUTING SIGNALS IN
THE CROSSHATCHED AREA (UPPER
LEFT-HAND QUADRANT) OF THE
PACKAGE UNLESS THERE IS A
GROUND PLANE BETWEEN THE
SIGNAL LINE AND THE PACKAGE.
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