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參數(shù)資料
| 型號： | DS1308U-18+T |
| 廠商： | Maxim Integrated Products |
| 文件頁數(shù)： | 5/16頁 |
| 文件大小： | 0K |
| 描述： | IC RTC 56BYTE NVRAM I2C 8UMAX |
| 標(biāo)準(zhǔn)包裝： | 3,000 |
| 類型： | 時鐘/日歷 |
| 特點(diǎn)： | 閏年，NVSRAM，方波輸出 |
| 存儲容量： | 56B |
| 時間格式： | HH:MM:SS（12/24 小時） |
| 數(shù)據(jù)格式： | YY-MM-DD-dd |
| 接口： | I²C，2 線串口 |
| 電源電壓： | 1.71 V ~ 5.5 V |
| 電壓 - 電源，電池： | 1.3 V ~ 5.5 V |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 8-TSSOP，8-MSOP（0.118"，3.00mm 寬） |
| 供應(yīng)商設(shè)備封裝： | 8-uMAX |
| 包裝： | 帶卷 (TR) |
DS1308
Low-Current I2C RTC with 56-Byte NV RAM
13
Maxim Integrated
If the difference between Ext-1Hz and Osc-1Hz is
greater than about 0.8%, Osc-1Hz runs unadjusted (see
Figure 4) and the loss of signal (LOS) is set, provided
the enable external clock input bit (ECLK) is set.
I2C Serial Port Operation
I2C Slave Address
The DS1308’s slave address byte is D0h. The first byte
sent to the device includes the device identifier and the
master must match the address assigned to the device.
I2C Definitions
The following terminology is commonly used to describe
I2C data transfers.
Master Device: The master device controls the slave
devices on the bus. The master device generates SCL
clock pulses and START and STOP conditions.
Slave Devices: Slave devices send and receive data
at the master’s request.
Bus Idle or Not Busy: Time between STOP and
START conditions when both SDA and SCL are inac-
tive and in their logic-high states. When the bus is idle
it often initiates a low-power mode for slave devices.
START Condition: A START condition is generated
by the master to initiate a new data transfer with a
slave. Transitioning SDA from high to low while SCL
remains high generates a START condition. See
Figure 1 for applicable timing.
STOP Condition: A STOP condition is generated
by the master to end a data transfer with a slave.
Transitioning SDA from low to high while SCL remains
high generates a STOP condition. See Figure 1 for
applicable timing.
Repeated START Condition: The master can use
a repeated START condition at the end of one data
transfer to indicate that it immediately initiates a new
data transfer following the current one. Repeated
STARTs are commonly used during read operations
to identify a specific memory address to begin a data
transfer. A repeated START condition is issued identi-
cally to a normal START condition. See Figure 1 for
applicable timing.
Bit Write: Transitions of SDA must occur during the low
state of SCL. The data on SDA must remain valid and
unchanged during the entire high pulse of SCL plus the
setup and hold time requirements (Figure 1). Data is
shifted into the device during the rising edge of the SCL.
Bit Read: At the end a write operation, the master
must release the SDA bus line for the proper amount
of setup time before the next rising edge of SCL dur-
ing a bit read (Figure 1). The device shifts out each
bit of data on SDA at the falling edge of the previous
SCL pulse and the data bit is valid at the rising edge
of the current SCL pulse. Remember that the master
generates all SCL clock pulses including when it is
reading bits from the slave.
Acknowledge (ACK and NACK): An acknowledge
(ACK) or not-acknowledge (NACK) is always the 9th
bit transmitted during a byte transfer. The device
receiving data (the master during a read or the slave
during a write operation) performs an ACK by trans-
mitting a zero during the 9th bit. A device performs
a NACK by transmitting a one during the 9th bit.
Timing for the ACK and NACK is identical to all other
bit writes. An ACK is the acknowledgment that the
device is properly receiving data. A NACK is used to
terminate a read sequence or as an indication that the
device is not receiving data.
Byte Write: A byte write consists of 8 bits of informa-
tion transferred from the master to the slave (most
significant bit first) plus a 1-bit acknowledgment from
the slave to the master. The 8 bits transmitted by the
master are done according to the bit write definition
and the acknowledgment is read using the bit read
definition.
Byte Read: A byte read is an 8-bit information transfer
from the slave to the master plus a 1-bit ACK or NACK
from the master to the slave. The 8 bits of information
that are transferred (most significant bit first) from the
slave to the master are read by the master using the
bit read definition, and the master transmits an ACK
using the bit write definition to receive additional data
Figure 6. Slave Address Byte
11
1
0R/W
0
MSB
LSB
READ/
WRITE BIT
DEVICE
IDENTIFIER
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| DS1308U-3 | 制造商:MAXIM 制造商全稱:Maxim Integrated Products 功能描述:Low-Current I2C RTC with 56-Byte NV RAM |
| DS1308U-3+ | 功能描述:實(shí)時時鐘 LOW CUR 3V I2C RTC RoHS:否 制造商:Microchip Technology 功能:Clock, Calendar. Alarm RTC 總線接口:I2C 日期格式:DW:DM:M:Y 時間格式:HH:MM:SS RTC 存儲容量:64 B 電源電壓-最大:5.5 V 電源電壓-最小:1.8 V 最大工作溫度:+ 85 C 最小工作溫度: 安裝風(fēng)格:Through Hole 封裝 / 箱體:PDIP-8 封裝:Tube |
| DS1308U-3+T | 功能描述:實(shí)時時鐘 LOW CUR 3V I2C RTC RoHS:否 制造商:Microchip Technology 功能:Clock, Calendar. Alarm RTC 總線接口:I2C 日期格式:DW:DM:M:Y 時間格式:HH:MM:SS RTC 存儲容量:64 B 電源電壓-最大:5.5 V 電源電壓-最小:1.8 V 最大工作溫度:+ 85 C 最小工作溫度: 安裝風(fēng)格:Through Hole 封裝 / 箱體:PDIP-8 封裝:Tube |
| DS1308U-33 | 制造商:MAXIM 制造商全稱:Maxim Integrated Products 功能描述:Low-Current I2C RTC with 56-Byte NV RAM |
| DS1308U-33+ | 功能描述:實(shí)時時鐘 LOW CUR 3.3V I2C RTC RoHS:否 制造商:Microchip Technology 功能:Clock, Calendar. Alarm RTC 總線接口:I2C 日期格式:DW:DM:M:Y 時間格式:HH:MM:SS RTC 存儲容量:64 B 電源電壓-最大:5.5 V 電源電壓-最小:1.8 V 最大工作溫度:+ 85 C 最小工作溫度: 安裝風(fēng)格:Through Hole 封裝 / 箱體:PDIP-8 封裝:Tube |
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