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參數(shù)資料
| 型號： | DS1243Y-120 |
| 廠商： | Maxim Integrated Products |
| 文件頁數(shù)： | 8/14頁 |
| 文件大小： | 0K |
| 描述： | IC NVSRAM 64KBIT 120NS 28DIP |
| 標準包裝： | 12 |
| 類型： | Phantom 計時芯片 |
| 特點： | 閏年 |
| 時間格式： | HH:MM:SS:hh（12/24 小時） |
| 數(shù)據(jù)格式： | YY-MM-DD-dd |
| 接口： | 并聯(lián) |
| 電源電壓： | 4.5 V ~ 5.5 V |
| 工作溫度： | 0°C ~ 70°C |
| 安裝類型： | 通孔 |
| 封裝/外殼： | 28-DIP 模塊（0.600"，15.24mm） |
| 供應商設備封裝： | 28-EDIP |
| 包裝： | 管件 |
| 其它名稱： | DS1243Y120 |
DS1243Y
3 of 14
RAM READ MODE
The DS1243Y executes a read cycle whenever WE (Write Enable) is inactive (high) and CE (Chip
Enable) is active (low). The unique address specified by the 13 address inputs (A0–A12) defines which of
the 8192 bytes of data is to be accessed. Valid data will be available to the eight data output drivers
within tACC (Access Time) after the last address input signal is stable, providing that CE and OE (Output
Enable) access times and states are also satisfied. If OE and CE access times are not satisfied, then data
access must be measured from the later occurring signal ( CE or OE ) and the limiting parameter is either
tCO for CE or tOE for OE rather than address access.
RAM WRITE MODE
The DS1243Y is in the write mode whenever the WE and CE signals are in the active (low) state after
address inputs are stable. The latter occurring falling edge of CE or WE will determine the start of the
write cycle. The write cycle is terminated by the earlier rising edge of CE or WE . All address inputs must
be kept valid throughout the write cycle. WE must return to the high state for a minimum recovery time
(tWR) before another cycle can be initiated. The OE control signal should be kept inactive (high) during
write cycles to avoid bus contention. However, if the output bus has been enabled ( CE and OE active)
then WE will disable the outputs in t ODW from its falling edge.
DATA RETENTION MODE
The DS1243Y provides full functional capability for VCC greater than VTP and write protects by 4.25V.
Data is maintained in the absence of VCC without any additional support circuitry. The nonvolatile static
RAM constantly monitors VCC. Should the supply voltage decay, the RAM automatically write protects
itself. All inputs to the RAM become “don’t care” and all outputs are high impedance. As VCC falls below
approximately 3.0V, the power switching circuit connects the lithium energy source to RAM to retain
data. During power-up, when VCC rises above approximately 3.0V, the power switching circuit connects
external VCC to the RAM and disconnects the lithium energy source. Normal RAM operation can resume
after VCC exceeds 4.5V.
See “Conditions of Acceptability” at www.maxim-ic.com/TechSupport/QA/ntrl.htm
FRESHNESS SEAL
Each DS1243Y is shipped from Maxim with its lithium energy source disconnected, insuring full energy
capacity. When VCC is first applied at a level greater than VTP, the lithium energy source is enabled for
battery backup operation.
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相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| DS1243Y120+ | 制造商:Maxim Integrated Products 功能描述: |
| DS1243Y-120+ | 功能描述:實時時鐘 64k NV SRAM w/Phantom Clock RoHS:否 制造商:Microchip Technology 功能:Clock, Calendar. Alarm RTC 總線接口:I2C 日期格式:DW:DM:M:Y 時間格式:HH:MM:SS RTC 存儲容量:64 B 電源電壓-最大:5.5 V 電源電壓-最小:1.8 V 最大工作溫度:+ 85 C 最小工作溫度: 安裝風格:Through Hole 封裝 / 箱體:PDIP-8 封裝:Tube |
| DS1243Y-120+ | 制造商:Maxim Integrated Products 功能描述:IC |
| DS1243Y-150 | 制造商:DALLAS 制造商全稱:Dallas Semiconductor 功能描述:64K NV SRAM with Phantom Clock |
| DS1243Y4120 | 制造商:Maxim Integrated Products 功能描述: |
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