參數(shù)資料
型號(hào)： DS1100Z-75/T&R
廠商： DALLAS SEMICONDUCTOR
元件分類： Delay Line
英文描述： SILICON DELAY LINE, TRUE OUTPUT, PDSO8
封裝： 0.150 INCH, SOIC-8
文件頁(yè)數(shù)： 45/50頁(yè)
文件大?。?/td> 136K
代理商： DS1100Z-75/T&R
DS1100
5 of 6
TERMINOLOGY
Period: The time elapsed between the leading edge of the first pulse and the leading edge of the
following pulse.
tWI (Pulse Width): The elapsed time on the pulse between the 1.5V point on the leading edge and the
1.5V point on the trailing edge or the 1.5V point on the trailing edge and the 1.5V point on the leading
edge.
tRISE (Input Rise Time): The elapsed time between the 20% and the 80% point on the leading edge of the
input pulse.
tFALL (Input Fall Time): The elapsed time between the 80% and the 20% point on the trailing edge of the
input pulse.
tPLH (Time Delay, Rising): The elapsed time between the 1.5V point on the leading edge of the input
pulse and the 1.5V point on the leading edge of any tap output pulse.
tPHL (Time Delay, Falling): The elapsed time between the 1.5V point on the trailing edge of the input
pulse and the 1.5V point on the trailing edge of any tap output pulse.
TEST SETUP DESCRIPTION
Figure 3 illustrates the hardware configuration used for measuring the timing parameters on the DS1100.
The input waveform is produced by a precision pulse generator under software control. Time delays are
measured by a time interval counter (20 ps resolution) connected between the input and each tap. Each
tap is selected and connected to the counter by a VHF switch control unit. All measurements are fully
automated, with each instrument controlled by a central computer over an IEEE 488 bus.
TEST CONDITIONS INPUT :
Ambient Temperature:
25°C ± 3°C
Supply Voltage (VCC):
5.0V ± 0.1V
Input Pulse:
High = 3.0V ± 0.1V
Low = 0.0V ± 0.1V
Source Impedance:
50 Ohm Max.
Rise and Fall Time:
3.0 ns Max. (measured between 0.6V and 2.4V)
Pulse Width:
500 ns
Period:
1 s
OUTPUT:
Each output is loaded with the equivalent of one 74F04 input gate. Delay is measured at the 1.5V level on
the rising and falling edge.
NOTE:
Above conditions are for test only and do not restrict the operation of the device under other data sheet
conditions.
相關(guān)PDF資料
PDF描述
DS1100U-125/T&R SILICON DELAY LINE, TRUE OUTPUT, PDSO8
DS1100U-250/T&R SILICON DELAY LINE, TRUE OUTPUT, PDSO8
DS1100Z-100/T&R SILICON DELAY LINE, TRUE OUTPUT, PDSO8
DS1100Z-35/T&R SILICON DELAY LINE, TRUE OUTPUT, PDSO8
DS1100Z-45/T&R SILICON DELAY LINE, TRUE OUTPUT, PDSO8
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