參數(shù)資料
型號: DS1100Z-200/T&R
廠商: DALLAS SEMICONDUCTOR
元件分類: Delay Line
英文描述: SILICON DELAY LINE, TRUE OUTPUT, PDSO8
封裝: 0.150 INCH, SOIC-8
文件頁數(shù): 23/50頁
文件大?。?/td> 136K
代理商: DS1100Z-200/T&R
DS1100
3 of 6
ABSOLUTE MAXIMUM RATINGS*
Voltage on Any Pin Relative to Ground
-1.0V to +7.0V
Operating Temperature
-40°C to +85°C
Storage Temperature
-55°C to +125°C
Soldering Temperature
260°C for 10 seconds
Short Circuit Output Current
50 mA for 1 second
* This is a stress rating only and functional operation of the device at these or any other conditions above
those indicated in the operation sections of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods of time may affect reliability.
DC ELECTRICAL CHARACTERISTICS
(-40°C to +85°C; VCC = 5.0V ± 5%)
PARAMETER
SYM
TEST CONDITION
MIN
TYP
MAX
UNITS
NOTES
Supply Voltage
VCC
4.75
5.00
5.25
V
5
High Level
Input Voltage
VIH
2.2
VCC = 0.5
V
5
Low Level
Input Voltage
VIL
-0.5
0.8
V
5
Input Leakage
Current
II
0.0V
≤V
I
≤V
CC
-1.0
1.0
uA
Active Current
ICC
VCC=Max; Period=Min.
30
50
mA
6, 8
High Level
Output Current
IOH
VCC=Min. VOH=4
-1
mA
Low Level
Output Current
IOL
VCC=Min. VOL=0.5
12
mA
AC ELECTRICAL CHARACTERISTICS
(TA = 25°C; VCC = 5V ± 5%)
PARAMETER
SYM
TEST CONDITION
MIN
TYP
MAX
UNITS
NOTES
Input
Pulse Width
tWI
20% of
Tap 5
tPLH
ns
25°C 5V
-2
Table 1
+2
ns
1, 3, 4, 7
0°C to 70°C
-3
Table 1
+3
ns
1, 2, 3, 4, 7
Input-to-Tap
Delay Tolerance
(Delays
≤40 ns)
tPLH
tPHL
-40°C to +85°C
-4
Table 1
+4
ns
1, 2, 3, 4, 7
25°C 5V
-5
Table 1
+5
%
1, 3, 4, 7
0°C to 70°C
-3
Table 1
+3
%
1, 2, 3, 4, 7
Input-to-Tap
Delay Tolerance
(Delays > 40 ns)
tPLH
tPHL
-40°C to +85°C
-8
Table 1
+8
%
1, 2, 3, 4, 7
Power-up Time
tPU
200
us
Input Period
Period
2(tWI)
ns
CAPACITANCE
(TA = 25°C)
PARAMETER
SYMBOL
MIN
TYP
MAX
UNITS
NOTES
Input Capacitance
CIN
5
10
pF
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