參數(shù)資料
型號: DS1077Z-100
廠商: DALLAS SEMICONDUCTOR
元件分類: Clock Generator
英文描述: 100 MHz, OTHER CLOCK GENERATOR, PDSO8
封裝: 0.150 INCH, SOIC-8
文件頁數(shù): 15/17頁
文件大?。?/td> 103K
代理商: DS1077Z-100
DS1077
7 of 17
(Refer to Table 5)
Table 5
Bit Value
Divisor (N)
0 000 000 000
**
2
0 000 000 001
3
--
1 111 111 111
1025
**Default Condition
BUS WORD
Name
---
B
WC
A2
A1
A0
Factory Default
0*0*0*0*
0
*These bits are reserved and must be set to “0” zero
A0,A1,A2
(Default Setting = 000)
These are the device select bits which determine the address of the device.
WC
(Default Setting WC=0)
This bit determines when/if the EEPROM is written to after register contents have been changed.
If WC = 0 the EEPROM is written automatically after a write register command.
If WC = 1 the EEPROM is only written when the “WRITE ” command is issued.
Regardless of the value of the WC bit the value of the BUS Register (A0,A1,A2) is always written
immediately to the EEPROM.
2-WIRE SERIAL DATA BUS
The DS1077 supports a bi-directional two-wire bus and data transmission protocol. A device that sends
data onto the bus is defined as a transmitter, and a device receiving data as a receiver. The device that
controls the message is called a "master". The devices that are controlled by the master are "slaves". The
bus must be controlled by a master device which generates the serial clock (SCL), controls the bus access,
and generates the START and STOP conditions. The DS1077 operates as a slave on the two-wire bus.
Connections to the bus are made via the open-drain I/O lines SDA* and SCL. A pullup resistor (5K) is
connected to SDA
The following bus protocol has been defined (See Figure 2):
Data transfer may be initiated only when the bus is not busy.
During data transfer, the data line must remain stable whenever the clock line is HIGH. Changes
in the data line while the clock line is high will be interpreted as control signals.
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