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參數(shù)資料
| 型號： | DS1023S-100 |
| 廠商： | DALLAS SEMICONDUCTOR |
| 元件分類： | Delay Line |
| 英文描述： | SILICON DELAY LINE, TRUE OUTPUT, PDSO16 |
| 封裝： | 0.300 INCH, SOIC-16 |
| 文件頁數(shù)： | 10/16頁 |
| 文件大?。?/td> | 261K |
| 代理商： | DS1023S-100 |
DS1023
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Applications can read the setting of the DS1023 Delay Line by connecting the serial output pin (Q) to the
serial input (D) through a resistor with a value of 1 to 10 kohms (Figure 2). Since the read process is
destructive, the resistor restores the value read and provides isolation when writing to the device. The
resistor must connect the serial output (Q) of the last device to the serial input (D) of the first device of a
daisy chain (Figure 1). For serial readout with automatic restoration through a resistor, the device used to
write serial data must go to a high impedance state.
To initiate a serial read, latch enable (LE) is taken to a logic 1 while serial clock (CLK) is at a logic 0.
After a waiting time (tEQV), bit 7 (MSB) appears on the serial output (Q). On the first rising (0 --> 1)
transition of the serial clock (CLK), bit 7 (MSB) is rewritten and bit 6 appears on the output after a time
tCQV. To restore the input register to its original state, this clocking process must be repeated eight times.
In the case of a daisy chain, the process must be repeated eight times per package. If the value read is
restored before latch enable (LE) is returned to logic 0, no settling time (tEDV) is required and the
programmed delay remains unchanged.
Since the DS1023 is a CMOS design, unused input pins (P3 - P7) must be connected to well-defined logic
levels; they must not be allowed to float. Serial output Q/P0 should be allowed to float if unused.
CASCADING MULTIPLE DEVICES (DAISY CHAIN) Figure 1
SERIAL READOUT Figure 2
REFERENCE DELAY
In all delay lines there is an inherent, or “step zero”, delay caused by the propagation delay through the
input and output buffers. In this device the step zero delay can be quite large compared to the delay step
size. To simplify system design a reference delay has been included on chip which may be used to
compensate for the step zero delay. In practice this means that if the device is supplied with a clock, for
example, the minimum programmed output delay is effectively zero with respect to the reference delay.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| DS1023S-500 | SILICON DELAY LINE, TRUE OUTPUT, PDSO16 |
| DS1077U-100 | 100 MHz, OTHER CLOCK GENERATOR, PDSO8 |
| DS1077U-125 | 125 MHz, OTHER CLOCK GENERATOR, PDSO8 |
| DS1077U-66 | 66.666 MHz, OTHER CLOCK GENERATOR, PDSO8 |
| DS1077Z-133 | 133.333 MHz, OTHER CLOCK GENERATOR, PDSO8 |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| DS1023S-100+ | 功能描述:延遲線/計時元素 Programmable 8-Bit 1ns Timing Element RoHS:否 制造商:Micrel 功能:Active Programmable Delay Line 傳播延遲時間:1000 ps 工作溫度范圍: 封裝 / 箱體:QFN-24 封裝:Tube |
| DS1023S-100+ | 制造商:Maxim Integrated Products 功能描述:DELAY LINE IC |
| DS1023S-100+T | 功能描述:延遲線/計時元素 Programmable 8-Bit 1ns Timing Element RoHS:否 制造商:Micrel 功能:Active Programmable Delay Line 傳播延遲時間:1000 ps 工作溫度范圍: 封裝 / 箱體:QFN-24 封裝:Tube |
| DS1023S-200 | 功能描述:延遲線/計時元素 Programmable 8-Bit 2ns Timing Element RoHS:否 制造商:Micrel 功能:Active Programmable Delay Line 傳播延遲時間:1000 ps 工作溫度范圍: 封裝 / 箱體:QFN-24 封裝:Tube |
| DS1023S-200/T&R | 制造商:Maxim Integrated Products 功能描述:PRG 8BIT DLAY 2.00NS STPS SO T&R - Tape and Reel 制造商:Maxim Integrated Products 功能描述:Delay Lines / Timing Elements Programmable 8-Bit 2ns Timing Element |
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