參數(shù)資料
型號(hào): DS1023-200
廠商: MAXIM INTEGRATED PRODUCTS INC
元件分類: Delay Line
英文描述: SILICON DELAY LINE, TRUE OUTPUT, PDIP16
封裝: 0.300 INCH, DIP-16
文件頁(yè)數(shù): 6/16頁(yè)
文件大?。?/td> 251K
代理商: DS1023-200
DS1023
14 of 16
TERMINOLOGY
Period: The time elapsed between the leading edge of the first pulse and the leading edge of the
following pulse.
tWI (Pulse Width): The elapsed time on the pulse between the 1.5V point on the leading edge and the 1.5V
point on the trailing edge, or the 1.5V point on the trailing edge and the 1.5V point on the leading edge.
tRISE (Input Rise Time): The elapsed time between the 20% and the 80% point on the leading edge of the
input pulse.
tFALL (Input Fall Time): The elapsed time between the 80% and the 20% point on the trailing edge of the
input pulse.
tD (Time Delay): The elapsed time between the 1.5V point on the edge of an input pulse and the 1.5V
point on the corresponding edge of the output pulse.
TIMING DIAGRAM: NON-LATCHED PARALLEL MODE
(P /S = 0, LE = 1) Figure 10
TIMING DIAGRAM: LATCHED PARALLEL MODE (P /S = 0) Figure 11
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