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參數(shù)資料
| 型號(hào)： | DS1004M-5 |
| 廠商： | DALLAS SEMICONDUCTOR |
| 元件分類： | Delay Line |
| 英文描述： | SILICON DELAY LINE, TRUE OUTPUT, PDIP8 |
| 封裝： | 0.300 INCH, DIP-8 |
| 文件頁數(shù)： | 3/6頁 |
| 文件大?。?/td> | 54K |
| 代理商： | DS1004M-5 |
DS1004
3 of 6
DS1004 TEST CIRCUIT Figure 1
TEST SETUP DESCRIPTION
Figure 1 illustrates the hardware configuration used for measuring the timing parameters of the DS1004.
The input waveform is produced by a precision pulse generator under software control. Time delays are
measured by a time interval counter (20 ps resolution) connected to the output. The DS1004 output taps
are selected and connected to the interval counter by a VHF switch control unit. All measurements are
fully automated with each instrument controlled by the computer over an IEEE 488 bus.
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