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參數資料
| 型號： | DM9348 |
| 文件頁數： | 75/158頁 |
| 文件大?。?/td> | 2668K |
| 代理商： | DM9348 |
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Switching Characteristics
V
CC
e a
5.0V, T
A
e a
25
§
C (See Section 1 for waveforms and load configurations)
C
L
e
15 pF
Symbol
Parameter
9338 (MIL)
DM9338 (COM)
Units
Min
Max
Min
Max
t
PLH
t
PHL
Propagation Delay
B
n
or C
n
to Z
n
40
35
13
18
40
35
ns
t
PLH
t
PHL
Propagation Delay
D
A
to Z
n
45
50
25
25
45
50
ns
t
PLH
t
PHL
Propagation Delay
CP to Z
n
35
30
18
13
35
30
ns
Functional Description
The 9338 8-bit multiple port register can be considered a 1-
bit slice of eight high speed working registers. Data can be
written into any one and read from any two of the eight
locations simultaneously. Master/slave operation eliminates
all race problems associated with simultaneous read/write
activity from the same location. When the clock input (CP) is
LOW data applied to the data input line (D
A
) enters the
selected master. This selection is accomplished by coding
the three write input select lines (A0–A2) appropriately.
Data is stored synchronously with the rising edge of the
clock pulse.
The information for each of the two slaved (output) latches
is selected by two sets of read address inputs (B0–B2 and
C0–C2). The information enters the slave while the clock is
HIGH and is stored while the clock is LOW. If Slave Enable
is LOW (SLE), the slave latches are continuously enabled.
The signals are available on the output pins (Z
B
and Z
C
).
The input bit selection and the two output bit selections can
be accomplished independently or simultaneously. The data
flows into the device, is demultiplexed according to the state
of the write address lines and is clocked into the selected
latch. The eight latches function as masters and store the
input data. The two output latches are slaves and hold the
data during the read operation. The state of each slave is
determined by the state of the master selected by its associ-
ated set of read address inputs.
The method of parallel expansion is shown inFigure a. One
9338 is needed for each bit of the required word length. The
read and write input lines should be connected in common
on all of the devices. This register configuration provides
two words of n-bits each at one time, where n devices are
connected in parallel.
Logic Symbol
TL/F/9794–2
V
CC
e
Pin 16
GND
e
Pin 8
TL/F/9794–4
FIGURE a. Parallel Expansion
3
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相關代理商/技術參數 |
參數描述 |
|---|---|
| DM9348J/883 | 制造商:National Semiconductor Corporation 功能描述:Parity Generator/Checker 12-Bit 16-Pin CDIP 制造商:National Semiconductor 功能描述:Parity Generator/Checker 12-Bit 16-Pin CDIP |
| DM9348J883 | 制造商:Texas Instruments 功能描述:* |
| DM9348J883QS | 制造商:NATIONAL 功能描述:NEW |
| DM9348W/883 | 制造商:Rochester Electronics LLC 功能描述:- Bulk |
| DM9368 | 制造商:FAIRCHILD 制造商全稱:Fairchild Semiconductor 功能描述:7-Segment Decoder/Driver/Latch with Constant Current Source Outputs |
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