參數(shù)資料
型號(hào)： DM9102
廠商： Electronic Theatre Controls, Inc.
英文描述： Single Chip Fast Ethernet NIC controller
中文描述： 單芯片快速以太網(wǎng)網(wǎng)卡控制器
文件頁數(shù)： 62/77頁
文件大小： 459K
代理商： DM9102
DM9102A
Single Chip Fast Ethernet NIC controller
62
Final
Version: DM9102A-DS-F03
August 28, 2000
If bit4 = 0, WOL is Active HIGH.
If bit4=1, WOL is Active LOW
If bit6 = 0, WOL is PULSE signal
If bit6=1, WOL is DC LEVEL signal.
Byte Offset (09): New_Capabilities_Enable
Bit0: Directly mapping to bit20 (New Capabilities) of the
PCICS
0
1
7
Byte Offset (14): PMC
Bit7~3: Directly mapping to bit15~11 of PMC (that is
bit31~27 of Power Management Register)
0
7
3
2
Bit2~0: Directly mapping to bit5~3 of PMC (that is bit21~19
of Power Management Register)
Byte Offset (15):
Bit7~4: Reserved
Bit3: Set to disable the output of PME# pin.
Bit2: Set to disable the output of WOL pin.
Bit1: Set to enable the link change wake up event.
Bit0: Set to enable the Magic packet wake up event.
0
3
4
7
Byte Offset (16): ID_BLOCK_CRC
0
7
This field is implemented to confirm the correct reading of
the EEPROM contents.
2. SROM Version
Current version number is 03.
3. Controller Count
The configuration ROM supports multiple controllers in one
board. Every controller has its unique controller information
block. Controller count indicates the number of controllers
put in the card.
4. Controller_X Information
Each controller has its information block to address its node
ID, GPR control, supported connect media types (Media
Information Block) and other application circuit information
block.
Controller Information Header
ITEM
Offset
0
6
7
Size
6
1
1
Node Address
Controller_x Number
Controller_x Info. Block Offset
5. Controller Information Body Pointed By Controller_X
Info Block Offset Item In Controller Information Header:
Item
Offset
0
2
3
4
4+n
Size
2
1
1
n
m
Connection Type Selected
GPR Control
Block Count
Block_1
:
* Connect Type Selected indicates the default connect
media type selected.
* GPR Control defines the input or output direction of GPR.
There are three types of block:
1. PHY Information Block (type=01)
2. Media Information Block (type=00)
3. Delay Period Block (type=80)
PHY information Block: (type=01)
Item
Block Length
Block Type(01)
PHY Number
GPR Initial Length(G_i)
GPR Initial Data
Reset Sequence Length(R_i)
Reset Data
Media Capabilities
Nway Advertisement
FDX Bit Map
Offset
0
1
2
3
4
4+G_i
5+G_i
5+G_i+R_i
7+G_i+R_i
9+G_i+R_i
Size
1
1
1
1
G_i
1
R_i
2
2
2
相關(guān)PDF資料
PDF描述
DM9102A Single Chip Fast Ethernet NIC controller
DM9102AF Single Chip Fast Ethernet NIC controller
DM9102AT Single Chip Fast Ethernet NIC controller
DM9108APPLICATIONENGINEERINGNOTESONE DM9108 Application Engineering notes one
DM9108APPLICATIONENGINEERINGNOTESTHREE DM9108 Application Engineering notes three
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
DM9102A 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Single Chip Fast Ethernet NIC controller
DM9102AF 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Single Chip Fast Ethernet NIC controller
DM9102AT 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Single Chip Fast Ethernet NIC controller
DM9102D 制造商:未知廠家 制造商全稱:未知廠家 功能描述:SINGLE CHIP FAST ETHEMET NIC CONTROLLER
DM9102DE 制造商:DAVICOM 制造商全稱:DAVICOM 功能描述:Single Chip Fast Ethernet NIC Controller
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