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參數(shù)資料
| 型號(hào)： | DLO3416 |
| 廠商： | SIEMENS A G |
| 元件分類： | 顯示用LED |
| 英文描述： | .270 4-character 5 x 7 Dot Matrix Alphanumeric Intelligent Display with Memory/Decoder/Drive |
| 中文描述： | 5X7 DOT MATRIX DISPLAY, HIGH EFFICIENCY RED, 6.9 mm |
| 文件頁(yè)數(shù)： | 4/6頁(yè) |
| 文件大小： | 222K |
| 代理商： | DLO3416 |
2–4
DLR/DLO/DLG3416
Display Blanking
Blank the display by loading a blank or space into each digit of
the display or by using the (BL) display blank input.
Setting the (BL) input low does not affect the contents of either
data or cursor memory. A flashing display can be achieved by
pulsing (BL). A flashing circuit can be constructed using a 555
a stable multivibrator. Figure 3 illustrates a circuit in which vary-
ing R2 (100K~10K) will have a flash rate of 1 Hz~10 Hz.
Figure 3. Flashing circuit using a 555
Figure 3a. Flashing (blanking) timing
555
Timer
R1
4.7 K
R2
100 K
C4
0.01
μ
F
C3
10
μ
F
VCC=5.0 V
To BL
Pin on
Display
1
2
3
4
8
7
6
5
Blanking Pulse Width
≈
50% Duty Factor
500 ms
~
2 Hz Blanking Frequency
1
0
~
The display can be dimmed by pulsing (BL) line at a frequency
sufficiently fast to not interfere with the internal clock. The dim-
ming signal frequency should be 2.5 KHz or higher. Dimming
the display also reduces power consumption.
An example of a simple dimming circuit using a 556 is illus-
trated in Figure 4. Adjusting potentiometer R3 will dim the dis-
play by changing the blanking pulse duty cycle.
Figure 4. Flashing circuit using a 555
Figure 4a. Flashing (blanking) timing
555
Timer
R1
4.7 K
R2
100 K
C4
0.01
μ
F
C3
10
μ
F
VCC=5.0 V
To BL
Pin on
Display
1
2
3
4
8
7
6
5
Blanking Pulse Width
≈
50% Duty Factor
500 ms
~
2 Hz Blanking Frequency
1
0
~
Figure 5. Internal block diagram
3 2 1 0
Display
Rows 0 to 6
Timing and Control Logic
Row Control Logic
&
Row Drivers
Row Decoder
RAM Read Logic
RAM
Memory
ROM
128 X 35 Bit
ASCII
Character
Decode
7 Bit ASCII Code
Column Data
D6
D5
D4
D3
D2
D1
D0
4480 bits
CUE
OSC
128
Counter
7
Counter
Column Enable
Latches and
Column Drivers
L
C
WR
A0
A1
Write
Address
4 X 7 bit
Columns 0 to 19
Address Lines
BL
Cursor
Memory
4 X 1 bit
Cursor Memory Bits 0 to 3
Decoder
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| DLG3416 | .270 4-character 5 x 7 Dot Matrix Alphanumeric Intelligent Display with Memory/Decoder/Drive |
| DLR3416 | .270 4-character 5 x 7 Dot Matrix Alphanumeric Intelligent Display with Memory/Decoder/Drive |
| DLP-IO16 | DLP-IO16 Development System |
| DLP-USB1 | USB to FIFO Parallel Interface Module |
| DLR5735 | 17.5 mm Single Character 5x7 Dot Matrix Alphanumeric Display |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| DLO34F | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Voltage-controlled TTL delay line oscillator |
| DLO-34F | 制造商:DATADELAY 制造商全稱:Data Delay Devices, Inc. 功能描述:GATED-DELAY LINE OSCILLATOR |
| DLO-34F-10 | 制造商:DATADELAY 制造商全稱:Data Delay Devices, Inc. 功能描述:GATED-DELAY LINE OSCILLATOR |
| DLO-34F-11 | 制造商:DATADELAY 制造商全稱:Data Delay Devices, Inc. 功能描述:GATED-DELAY LINE OSCILLATOR |
| DLO-34F-12 | 制造商:DATADELAY 制造商全稱:Data Delay Devices, Inc. 功能描述:GATED-DELAY LINE OSCILLATOR |
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