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參數(shù)資料
| 型號： | DLKPC192S |
| 英文描述： | 10Gbps Ethernet LAN Physical Coding Sublayer (PCS) Device |
| 中文描述： | 10Gbps的以太網(wǎng)物理編碼子層（PCS）設備 |
| 文件頁數(shù)： | 5/25頁 |
| 文件大小： | 360K |
| 代理商： | DLKPC192S |
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SLLS536
–
AUGUST 2002
5
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
Signal Terminal Functions (Continued)
XSBI interface terminals
SIGNAL
LOCATION
TYPE
DESCRIPTION
TXCP/TXCN
H17, H16
LVDS output
XSBI transmit clock. Differential output clock. The data on TXP[0:15]/TXN[0:15] is
transferred on the rising edge of the transmit data clock. Nominal frequency of
TXCP/TXCN is 644.53125 MHz.
TX[0:15]P/N
D17, D16, E17, E16,
F14, E14, G13, F13,
G17, G16, H14, H13,
J14, J13, J16, J15,
K15, K14, L14, L13,
L17, L16, M16, M15,
M13, M14, N15, N14,
P15, P14, P16, P17
LVDS output
XSBI transmit data. Parallel data on this bus is clocked on the rising edge of TXCP.
RXCP/RXCN
U7, T7
LVDS input
XSBI receive clock. Differential input clock. The data on RXP[0:15]/RXN[0:15] is
latched on the rising edge of this clock. Please note, the positive side of this differential
clock (RXCP) needs to rise
in the middle of the data
. Nominal frequency of
RXCP/RXCN is 644.53125 MHz. There is a 100-
on-chip termination resistor placed
differentially between the terminals of each terminal pair.
RX[0:15]P/N
R13, P13, U13, T13,
P12, N12, U12, T12,
P11, N11, T10, R10,
N9, N10, T9, R9,
P8, N8, T8, U8,
P7, N7, P6, N6,
T5, T6, N5, P5,
T4, U4, P4, R4
LVDS input
XSBI receive data. Parallel data on this bus is valid on the rising edge of RXCP/RXCN.
There is a 100-
on-chip termination resistor placed differentially between the
terminals of each terminal pair.
management data interface
SIGNAL
LOCATION
TYPE
DESCRIPTION
MDIO
U17
LVTTL
input/output
Management data input/output. MDIO is the bidirectional serial data path for the
transfer of management data to and from the DLKPC192S device.
MDC
U16
LVTTL input
Management data clock. MDC is the clock for the transfer of management data to and
from the protocol device.
DVAD[0:4]
B17, A17, A16, A15,
B15
LVTTL input
Management address. These terminals determine the device address on the MDIO
interface to which the DLKPC192S responds. The DLKPC192S only responds to valid
commands that contain a device address equal to the value seen on these terminals.
reference clock terminals
SIGNAL
LOCATION
TYPE
DESCRIPTION
RFCP/RFCN
T11, U11
LVDS input
XGMII receive reference clock. Differential reference clock for generation of XGMII
receive interface functions. Nominal frequency of RFCP/RFCN is 156.25 MHz. There
is a 100-
on-chip termination resistor placed differentially between the two terminals.
XSBI transmit reference clock. Differential reference clock for generation of XSBI
transmit interface functions. Nominal frequency of XBICP/XBICN is 644.53125 MHz.
There is a 100-
on-chip termination resistor placed differentially between the two
terminals
XBICP/XBICN
T14, U14
LVDS input
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