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參數(shù)資料
| 型號(hào)： | DC956A |
| 廠商： | Linear Technology |
| 文件頁(yè)數(shù)： | 34/40頁(yè) |
| 文件大小： | 0K |
| 描述： | BOARD DELTA SIGMA ADC LTC2485 |
| 軟件下載： | QuikEval System |
| 設(shè)計(jì)資源： | DC956A Design File DC956A Schematic |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 系列： | Easy Drive™, QuikEval™ |
| ADC 的數(shù)量： | 1 |
| 位數(shù)： | 24 |
| 采樣率（每秒）： | 6.8 |
| 數(shù)據(jù)接口： | I²C，串行 |
| 工作溫度： | 0°C ~ 70°C |
| 已用 IC / 零件： | LTC2485 |
| 已供物品： | 板 |
| 相關(guān)產(chǎn)品： | LTC2485CDD#TRPBF-ND - IC ADC 24BIT I2C 10-DFN LTC2485IDD#TRPBF-ND - IC ADC 24BIT I2C 10-DFN LTC2485IDD#PBF-ND - IC ADC 24BIT I2C 10-DFN LTC2485CDD#PBF-ND - IC ADC 24BIT I2C 10-DFN |
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LTC2485
4
2485fc
ANALOG INPUT AND REFERENCE The l denotes the specications which apply over the full operating
temperature range, otherwise specications are at TA = 25°C. (Note 3)
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
CS (IN+)IN+ Sampling Capacitance
11
pF
CS (IN–)IN– Sampling Capacitance
11
pF
CS (VREF)VREF Sampling Capacitance
11
pF
IDC_LEAK (IN+)IN+ DC Leakage Current
Sleep Mode, IN+ = GND
●
–10
1
10
nA
IDC_LEAK (IN–)IN– DC Leakage Current
Sleep Mode, IN– = GND
●
–10
1
10
nA
IDC_LEAK (VREF)REF+, REF– DC Leakage Current
Sleep Mode, VREF = VCC
●
–100
1
100
nA
I2C DIGITAL INPUTS AND DIGITAL OUTPUTS The l denotes the specications which apply over
the full operating temperature range, otherwise specications are at TA = 25°C. (Note 3)
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
VIH
High Level Input Voltage
●
0.7VCC
V
VIL
Low Level Input Voltage
●
0.3VCC
V
VIL(CA1)
Low Level Input Voltage for Address Pin
●
0.05VCC
V
VIH(CA0/f0,CA1)
High Level Input Voltage for Address Pins
●
0.95VCC
V
RINH
Resistance from CA0/f0, CA1 to VCC to Set
Chip Address Bit to 1
●
10
kΩ
RINL
Resistance from CA1 to GND to Set Chip
Address Bit to 0
●
10
kΩ
RINF
Resistance from CA0/f0, CA1 to VCC or
GND to Set Chip Address Bit to Float
●
2
MΩ
II
Digital Input Current
●
–10
10
μA
VHYS
Hysteresis of Schmitt Trigger Inputs
(Note 5)
0.05VCC
V
VOL
Low Level Output Voltage SDA
I = 3mA
●
0.4
V
tOF
Output Fall Time from VIHMIN to VILMAX
Bus Load CB 10pF to 400pF (Note 14)
●
20+0.1CB
250
ns
tSP
Input Spike Suppression
●
50
ns
IIN
Input Leakage
0.1VCC ≤ VIN ≤ VCC
●
1μA
CI
Capacitance for Each I/O Pin
●
10
pF
CB
Capacitance Load for Each Bus Line
●
400
pF
CCAX
External Capacitive Load On-Chip Address
Pins (CA0/f0,CA1) for Valid Float
●
10
pF
VIH(EXT,OSC)
High Level CA0/f0 External Oscillator
2.7V ≤ VCC < 5.5V
●
VCC – 0.5V
V
VIL(EXT,OSC)
Low Level CA0/f0 External Oscillator
2.7V ≤ VCC < 5.5V
●
0.5
V
POWER REQUIREMENTS The l denotes the specications which apply over the full operating temperature
range, otherwise specications are at TA = 25°C. (Note 3)
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
VCC
Supply Voltage
●
2.7
5.5
V
ICC
Supply Current
Conversion Mode (Note 11)
Sleep Mode (Note 11)
●
160
1
250
2
μA
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