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參數(shù)資料
| 型號： | DC955A |
| 廠商： | Linear Technology |
| 文件頁數(shù)： | 8/34頁 |
| 文件大?。?/td> | 0K |
| 描述： | BOARD DELTA SIGMA ADC LTC2483 |
| 軟件下載： | QuikEval System |
| 設(shè)計(jì)資源： | DC955A Design File DC955A Schematic |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 系列： | Easy Drive™, QuikEval™ |
| ADC 的數(shù)量： | 1 |
| 位數(shù)： | 16 |
| 采樣率（每秒）： | 6.8 |
| 數(shù)據(jù)接口： | I²C，串行 |
| 工作溫度： | 0°C ~ 70°C |
| 已用 IC / 零件： | LTC2483 |
| 已供物品： | 板 |
| 相關(guān)產(chǎn)品： | LTC2483IDD#TRPBF-ND - IC ADC 16BIT I2C 10-DFN LTC2483CDD#TRPBF-ND - IC ADC 16BIT I2C 10-DFN LTC2483IDD#PBF-ND - IC ADC 16BIT I2C 10-DFN LTC2483CDD#PBF-ND - IC ADC 16BIT I2C 10-DFN |
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LTC2483
2483fc
normal mode rejection in a frequency range of fEOSC/5120
±4% and its harmonics. The normal mode rejection as a
function of the input frequency deviation from fEOSC/5120
is shown in Figure 6.
applicaTions inFormaTion
WheneveranexternalclockisnotpresentattheCA0/F0pin,
the converter automatically activates its internal oscillator
and enters the internal conversion clock mode. CA0/F0
may be tied HIGH or left floating in order to set the chip
address. The LTC2483 operation will not be disturbed if
the change of conversion clock source occurs during the
sleep state or during the data output state while the con-
verter uses an external serial clock. If the change occurs
during the conversion state, the result of the conversion in
progress may be outside specifications but the following
conversions will not be affected.
Table 4 summarizes the duration of the conversion state
of each state and the achievable output data rate as a
function of fEOSC.
DIFFERENTIAL INPUT SIGNAL FREQUENCY
DEVIATION FROM NOTCH FREQUENCY fEOSC/5120(%)
–12
–8
–4
0
4
8
12
NORMAL
MODE
REJECTION
(dB)
2483 F06
–80
–85
–90
–95
–100
–105
–110
–115
–120
–125
–130
–135
–140
Figure 6. LTC2483 Normal Mode Rejection When
Using an External Oscillator
Ease of Use
The LTC2483 data output has no latency, filter settling
delay or redundant data associated with the conversion
cycle. There is a one-to-one correspondence between the
conversion and the output data. Therefore, multiplexing
multiple analog voltages is easy.
The LTC2483 performs offset and full-scale calibrations
every conversion cycle. This calibration is transparent to
the user and has no effect on the cyclic operation described
above. The advantage of continuous calibration is extreme
stability of offset and full-scale readings with respect to
time, supply voltage change and temperature drift.
Power-Up Sequence
The LTC2483 automatically enters an internal reset state
when the power supply voltage VCC drops below ap-
proximately 2V. This feature guarantees the integrity of
the conversion result.
When the VCC voltage rises above this critical threshold,
the converter creates an internal power-on reset (POR)
signal with a duration of approximately 4ms. The POR
signalclearsallinternalregisters.FollowingthePORsignal,
the LTC2483 starts a normal conversion cycle and follows
the succession of states described in Figure 1. The first
conversion result following POR is accurate within the
specifications of the device if the power supply voltage is
restored within the operating range (2.7V to 5.5V) before
the end of the POR time interval.
Reference Voltage Range
The LTC2483 external reference voltage range is 0.1V
to VCC. The converter output noise is determined by
Table 4. LTC2483 State Duration
STATE
OPERATING MODE
DURATION
CONVERSION
Internal Oscillator
50Hz/60Hz Rejection
147ms, Output Data Rate ≤ 6.8 Readings/s
External Oscillator
CA0/F0 = External Oscillator with Frequency
fEOSC Hz (fEOSC/5120 Rejection)
41036/fEOSCs, Output Data Rate ≤ fEOSC/41036 Readings/s
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